z85230drv.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* z85230Drv.h - header file for z85230Drv module */

/* Copyright 2000-2003 Dy4 Systems, Inc. */

/*
modification history
--------------------
01d 07jun05,dle support 183 Serial IPM V2
01c 22sep03,aak provisions for generic SIO API
01b 20dec02,aak	expand Z85230PROTOCOL structure for FPGA callbacks 
01a 12aug02,aak	create from VME-179 
*/

#ifndef Z85230DRV_H
#define Z85230DRV_H

#ifdef __cplusplus
extern "C" {
#endif

#include <vxWorks.h>
#include <iosLib.h>
#include <sioLib.h>
#include <semLib.h>

#include "boardName.h"

/* Generic Dy 4 SIO include file */
#include "drv/sio/sioDy4Drv.h"

/* Driver-specific include files */
#include "drv/sio/z85230Err.h"
#include "drv/sio/z85230OS.h"
#include "drv/sio/z85230Buf.h"
#include "drv/sio/z85230Hw.h"
#include "drv/sio/z85230Async.h"
#include "drv/sio/z85230RHDLC.h"

#ifndef VME_181
IMPORT UINT32 sysGetSerialMemBaseAdrs(void);
#endif

/* preprocessor macros */

/* max & min baud rates for async & sync modes */

#ifdef VME_181
#define Z85230_MAX_ASYNC_BAUDRATE    156250
#define Z85230_MIN_ASYNC_BAUDRATE    100
#else
#define Z85230_MAX_ASYNC_BAUDRATE    115200
#define Z85230_MIN_ASYNC_BAUDRATE    1200
#endif

#define Z85230_MAX_SYNC_BAUDRATE     2500000
#define Z85230_MIN_SYNC_BAUDRATE     9600

/* protocols */

#define Z85230_PROTOCOL_ASYNC       SIO_DY4_ASYNC
#define Z85230_PROTOCOL_RHDLC       SIO_DY4_RHDLC

/* ioctls */

/*
 * The driver defines a set of proprietary commands to enhance
 * the device configuration options. The constants below
 * are defined to maintain backward compatibility.
 * They should not be used in new designs.
 * See generic Dy 4 SIO include file sioDy4Drv.h 
 */

#define Z85230_IOCTL_BASE           (SIO_DY4_IOCTL_BASE)

#define Z85230_SET_PROTOCOL         (SIO_DY4_SET_PROTOCOL)

#define Z85230_SET_TX_BUFFERCAPACITY  (SIO_DY4_SET_TXBUF_CAPACITY)
#define Z85230_GET_TX_BUFFERCAPACITY  (SIO_DY4_GET_TXBUF_CAPACITY)

#define Z85230_SET_RX_BUFFERCAPACITY  (SIO_DY4_SET_RXBUF_CAPACITY)
#define Z85230_GET_RX_BUFFERCAPACITY  (SIO_DY4_GET_RXBUF_CAPACITY)

#define Z85230_SET_BLOCKING         SIO_DY4_SET_BLOCKING
#define Z85230_GET_BLOCKING         SIO_DY4_GET_BLOCKING

#define Z85230_SET_RXADDR          SIO_DY4_SET_RXADDR
#define Z85230_GET_RXADDR          SIO_DY4_GET_RXADDR

#define Z85230_SET_HALFDUPLEX      SIO_DY4_SET_HALFDUPLEX
#define Z85230_GET_HALFDUPLEX      SIO_DY4_GET_HALFDUPLEX

#define Z85230_SET_CHK_ADDR        SIO_DY4_SET_CHK_ADDR
#define Z85230_GET_CHK_ADDR        SIO_DY4_GET_CHK_ADDR

#define Z85230_SET_CHK_CRC         SIO_DY4_SET_CHK_CRC
#define Z85230_GET_CHK_CRC         SIO_DY4_GET_CHK_CRC

#define Z85230_SET_WRITE_TO        SIO_DY4_SET_WRITE_TO
#define Z85230_GET_WRITE_TO        SIO_DY4_GET_WRITE_TO

#define Z85230_SET_READ_TO         SIO_DY4_SET_READ_TO
#define Z85230_GET_READ_TO         SIO_DY4_GET_READ_TO

#define Z85230_SET_EXT_RX_CLK       (SIO_DY4_SET_RXCLK_EXT)
#define Z85230_GET_EXT_RX_CLK       (SIO_DY4_GET_RXCLK_EXT)

#define Z85230_SET_TX_CLK_OFF_DELAY (SIO_DY4_SET_TXCLK_OFF_DELAY)
#define Z85230_GET_TX_CLK_OFF_DELAY (SIO_DY4_GET_TXCLK_OFF_DELAY)

#define Z85230_SET_CRC_POLY         (SIO_DY4_SET_CRC_POLY)
#define Z85230_GET_CRC_POLY         (SIO_DY4_GET_CRC_POLY)

#define Z85230_OPEN                 (SIO_OPEN)
#define Z85230_HUP                  (SIO_HUP)

#define Z85230_MODE_GET             (SIO_MODE_GET)
#define Z85230_MODE_SET             (SIO_MODE_SET)

#define Z85230_GET_BAUDRATE         (SIO_BAUD_GET)
#define Z85230_SET_BAUDRATE         (SIO_BAUD_SET)

#define Z85230_HW_OPTS_GET          (SIO_HW_OPTS_GET)
#define Z85230_HW_OPTS_SET          (SIO_HW_OPTS_SET)

#define Z85230_AVAIL_MODES_GET      (SIO_AVAIL_MODES_GET)

#define Z85230_FLUSH                (SIO_DY4_FLUSH)

/* channels */

#define Z85230_CHANNEL_A (SCC_CHANNEL_A)
#define Z85230_CHANNEL_B (SCC_CHANNEL_B)

#define Z85230_NUM_CHANNELS (2)

#define Z85230_RX_PRIO		(60)	/* Async Rx task priority */

/* transfer modes */
#define Z85230_MODE_INT             (SIO_DY4_MODE_INT)
#define Z85230_MODE_DMA             (SIO_DY4_MODE_DMA)

/* CRC Polynomials */
#define Z85230_SDLC_POLY     (SIO_DY4_POLY_SDLC)    /* default */
#define Z85230_CRC16_POLY    (SIO_DY4_POLY_CRC16)    

/* device and channel structures */

struct _Z85230_CHAN;

typedef struct {
  int protocol;  /* which protocol is in use */
  int status;    /* error level */
  int (*open)( struct _Z85230_CHAN * channel );
  int (*close)( struct _Z85230_CHAN * channel );
  int (*read)( struct _Z85230_CHAN * channel, 
	       unsigned char * bytes, int size );
  int (*write)( struct _Z85230_CHAN * channel, 
		unsigned char * bytes, int size );
  int (*ioctl)( struct _Z85230_CHAN * channel,
		int command, int param );
  void (*txInt)( struct _Z85230_CHAN * channel,
		 unsigned char intStatus );
  void (*rxInt)( struct _Z85230_CHAN * channel,
		 unsigned char intStatus  );
  void (*exInt)( struct _Z85230_CHAN * channel,
		 unsigned char intStatus  );
  void (*rxDmaInt)( struct _Z85230_CHAN * channel );
  void (*txDmaInt)( struct _Z85230_CHAN * channel );

  void (*rxFpgaInt)( struct _Z85230_CHAN * channel ); /* aak: DMA mode only  */
  void (*txFpgaInt)( struct _Z85230_CHAN * channel ); /* aak: DMA mode only  */
#ifndef VME_181
  void (*timeoutFpgaInt)( struct _Z85230_CHAN * channel ); /* dle: DMA async mode only  */
#endif

} Z85230PROTOCOL;

typedef struct _Z85230_CHAN {
  /* misc values */

  SEM_ID readSem;       /* used to implement timeouts on
			 * blocking reads
			 */
  SEM_ID writeSem;      /* used to implement timeouts on
			 * blocking writes
			 */

  int    channel;       /* Z85230_CHANNEL_A or Z85230_CHANNEL_B */
  char * name;          /* name of the channel */
  
  int    isOpen;        /* the number of sucesssful opens() on this channel */

  /* interrupt/polled mode configuration info */
  
  int    blocking;      /* [TRUE | FALSE] */
  int    writeTimeout;  /* how long before we give up on blocking write */
  int    readTimeout;   /* how long before we give up on blocking read  */

  /* status */

  int    readError;     /* last read error */
  int    writeError;    /* last write error */
  int    openError;     /* last open error */
  int    closeError;    /* last close error */
  int    error;         /* any error not of the other types */

  Z8530_CHAN      hw;   

  Z85230PROTOCOL protocol;      /* describes current protocol in use */

  Z85230BUF_STREAM txStreamBuf; /* ring buffer used for transmission 
				  * of stream data */
  Z85230BUF_STREAM rxStreamBuf; /* ring buffer used for reception 
				  * of stream data */

  Z85230BUF_FRAMES txFrameBuf;  /* ring buffer used for transmission 
				  * of frame data */
  Z85230BUF_FRAMES rxFrameBuf;  /* ring buffer used for reception 
				  * of frame data */
} Z85230_CHAN;

typedef struct {
  /* must be first */
  DEV_HDR devHdr;

  Z85230_CHAN channel;
} Z85230_DEV;

#define SCC_DMA_CHAN_RX	 ((channel->channel==SCC_CHANNEL_A)?SCC_RXA_DMA_CHAN:SCC_RXB_DMA_CHAN)
#define SCC_DMA_CHAN_TX	 ((channel->channel==SCC_CHANNEL_A)?SCC_TXA_DMA_CHAN:SCC_TXB_DMA_CHAN)

/* global variables */

#ifndef Z85230DRV_C
extern int gZ85230ChannelAStatus;
extern int gZ85230ChannelBStatus;

extern Z85230_CHAN * gZ85230Channels[ Z85230_NUM_CHANNELS ];
extern void * gZ85230Base;
extern void * gZ85230Gt64130Base;
#endif /* Z85230DRV_C */

STATUS z85230Drv( int reserved );
STATUS z85230DevCreat( char * devName, int channel );
STATUS z85230DrvRemove( int force_close );
STATUS z85230DevRemove( char * devName );

int z85230DrvOpen( DEV_HDR * pDevHdr, char * pName, int mode );
STATUS z85230DrvClose( Z85230_DEV * pDev );
int z85230DrvIoctl( Z85230_DEV * pDev, int command, int arg );
int z85230DrvRead( Z85230_DEV * pDev, unsigned char * pBuf, int nBytes );
int z85230DrvWrite( Z85230_DEV * pDev, unsigned char * pBuf, int nBytes );

#ifdef __cplusplus
}
#endif

#endif /* Z85230DRV_H */