fpgatimer.c

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

/* fpgaTimer.c - FPGA timer library */

/**********************************************************************
 *
 *   Copyright (c) 2003-2004, Dy 4 Systems All rights reserved.
 *   This Source Code is the Property of Dy 4 Systems Inc. and can
 *   only be used in accordance with Source Code License
 *   Agreement of Dy 4 Systems Inc. dba (doing business as) 
 *   CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING, "CWCEC". 
 *
 **********************************************************************/

/*
modification history
--------------------
01a,05nov04,tis     created based on DY4182 fpgaTimer.c v1a
01b,16nov04,jb      update byte ordering for fpgaTimerRead/load
*/
#include <vxWorks.h>

#include "h/drv/dy4/boardName.h"

#ifdef CCA145
#include "cca145.h"
#include "fpga145.h"
#endif

#ifdef VME_183
#include "cwv183.h"
#include "fpga183.h"
#endif


#include "h/drv/timer/fpgaTimer.h"

IMPORT void   sysOutByte (ULONG, UCHAR);
IMPORT UCHAR  sysInByte (ULONG);


/*******************************************************************************
* fpgaTimerHwInit - Initialize FPGA timers
*
* DESCRIPTION: Clear all FPGA timer INTs by clearing the INT register bit 
*
* INPUT:
*
* RETURN:
*
*/
void fpgaTimerHwInit()
{
    int i;

    if (sysProcId == CPU_ID_0)
    {
        for (i = IOFPGA_TIMER0_0; i <= IOFPGA_TIMER0_2; i++)
            fpgaTimerIntClear(i);
    }
    else
    {
        for (i = IOFPGA_TIMER1_0; i <= IOFPGA_TIMER1_2; i++)
            fpgaTimerIntClear(i);
    }
}


/*******************************************************************************
* fpgaTimerIntClear - Clear a FPGA timer INT
*
* DESCRIPTION: Clear the FPGA timer INT by clearing the INT register bit 
*
* INPUT:
*
* RETURN:
*
*/
BSP_STATUS fpgaTimerIntClear(IOFPGA_TIMER timer)
{
    unsigned char value;

    if (timer <= IOFPGA_TIMER_START && timer >= IOFPGA_TIMER_END)
        return BSP_INVALID_PARAM;

    if (((timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2) && (sysProcId != CPU_ID_0)) ||
        ((timer >= IOFPGA_TIMER1_0 && timer <= IOFPGA_TIMER1_2) && (sysProcId != CPU_ID_1)))
        return BSP_INVALID_PARAM;

    value = (FPGA_TIMER_INTSTAT_SET0_TMR0 << timer);
    sysOutByte((ULONG)FPGA_TIMER_INTSTAT, value);

    return BSP_OK;
}


/*******************************************************************************
* fpgaTimerStart - Start a FPGA timer
*
* DESCRIPTION: Start the FPGA timer by writing to control register bit
*
* INPUT:
*
* RETURN:
*
*/
BSP_STATUS fpgaTimerStart(IOFPGA_TIMER timer)
{
    unsigned char value;
    unsigned int regAdrs;

    if (timer <= IOFPGA_TIMER_START && timer >= IOFPGA_TIMER_END)
        return BSP_INVALID_PARAM;

    if (((timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2) && (sysProcId != CPU_ID_0)) ||
        ((timer >= IOFPGA_TIMER1_0 && timer <= IOFPGA_TIMER1_2) && (sysProcId != CPU_ID_1)))
        return BSP_INVALID_PARAM;

    if (timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2)
    {
        regAdrs = (ULONG)FPGA_SET0_TMR_CTRL;
    }
    else
    {
        regAdrs = (ULONG)FPGA_SET1_TMR_CTRL;
        timer -= IOFPGA_TIMER1_0;
    }

    value = sysInByte((ULONG)regAdrs);
    value |= (FPGA_SET0_TMR_CTRL_TMR0_ENBL << timer);
    sysOutByte((ULONG)regAdrs, value);

    return BSP_OK;
}


/*******************************************************************************
* fpgaTimerStop - Stop a FPGA timer
*
* DESCRIPTION: Stop the FPGA timer by writing to control register bit 
*
* INPUT:
*
* RETURN:
*
*/
BSP_STATUS fpgaTimerStop(IOFPGA_TIMER timer)
{
    unsigned char value;
    unsigned int regAdrs;

    if (timer <= IOFPGA_TIMER_START && timer >= IOFPGA_TIMER_END)
        return BSP_INVALID_PARAM;

    if (((timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2) && (sysProcId != CPU_ID_0)) ||
        ((timer >= IOFPGA_TIMER1_0 && timer <= IOFPGA_TIMER1_2) && (sysProcId != CPU_ID_1)))
        return BSP_INVALID_PARAM;

    if (timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2)
    {
        regAdrs = (ULONG)FPGA_SET0_TMR_CTRL;
    }
    else
    {
        regAdrs = (ULONG)FPGA_SET1_TMR_CTRL;
        timer -= IOFPGA_TIMER1_0;
    }
    value = sysInByte((ULONG)regAdrs);
    value &= ~(FPGA_SET0_TMR_CTRL_TMR0_ENBL << timer);
    sysOutByte((ULONG)regAdrs, value);


    return BSP_OK;
}

/*******************************************************************************
* fpgaTimerEnableSnapshot -
*
* DESCRIPTION:
*
* INPUT:
*
* RETURN:
*
*/
BSP_STATUS fpgaTimerEnableSnapshot(IOFPGA_TIMER timer)
{
    unsigned char value;
    unsigned int regAdrs;

    if (timer <= IOFPGA_TIMER_START && timer >= IOFPGA_TIMER_END)
        return BSP_INVALID_PARAM;

    if (((timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2) && (sysProcId != CPU_ID_0)) ||
        ((timer >= IOFPGA_TIMER1_0 && timer <= IOFPGA_TIMER1_2) && (sysProcId != CPU_ID_1)))
        return BSP_INVALID_PARAM;

    if (timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2)
    {
        regAdrs = (ULONG)FPGA_SET0_TMR_CTRL;
    }
    else
    {
        regAdrs = (ULONG)FPGA_SET1_TMR_CTRL;
        timer -= IOFPGA_TIMER1_0;
    }

    value = sysInByte((ULONG)regAdrs);
    value |= (FPGA_SET0_TMR_CTRL_TMR0_ENBL << (timer + FPGA_CTRL_TMR0_SNAPSHOT_OFFSET));
    sysOutByte((ULONG)regAdrs, value);

    return BSP_OK;
}

/*******************************************************************************
* fpgaTimerDisableSnapshot -
*
* DESCRIPTION:
*
* INPUT:
*
* RETURN:
*
*/
BSP_STATUS fpgaTimerDisableSnapshot(IOFPGA_TIMER timer)
{
    unsigned char value;
    unsigned int regAdrs;

    if (timer <= IOFPGA_TIMER_START && timer >= IOFPGA_TIMER_END)
        return BSP_INVALID_PARAM;

    if (((timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2) && (sysProcId != CPU_ID_0)) ||
        ((timer >= IOFPGA_TIMER1_0 && timer <= IOFPGA_TIMER1_2) && (sysProcId != CPU_ID_1)))
        return BSP_INVALID_PARAM;

    if (timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2)
    {
        regAdrs = (ULONG)FPGA_SET0_TMR_CTRL;
    }
    else
    {
        regAdrs = (ULONG)FPGA_SET1_TMR_CTRL;
        timer -= IOFPGA_TIMER1_0;
    }
    value = sysInByte((ULONG)regAdrs);
    value &= ~(FPGA_SET0_TMR_CTRL_TMR0_ENBL << (timer + FPGA_CTRL_TMR0_SNAPSHOT_OFFSET));
    sysOutByte((ULONG)regAdrs, value);


    return BSP_OK;
}
/*******************************************************************************
* fpgaTimerLoad - Load a value to the FPGA timer
*
* DESCRIPTION: Load the FPGA timer by writing two 8-bit values to the LSB and
*              MSB of the timer register.
*
* INPUT:
*
* RETURN:
*
*/
BSP_STATUS fpgaTimerLoad(IOFPGA_TIMER timer, unsigned int count)
{
    unsigned int regAdrs;


    UINT8 countByte;
    ULONG countAddr;


    if (timer <= IOFPGA_TIMER_START && timer >= IOFPGA_TIMER_END)
        return BSP_INVALID_PARAM;

    if (((timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2) && (sysProcId != CPU_ID_0)) ||
        ((timer >= IOFPGA_TIMER1_0 && timer <= IOFPGA_TIMER1_2) && (sysProcId != CPU_ID_1)))
        return BSP_INVALID_PARAM;

    /* Make sure that the timer is disabled before writing to the interval registers */
    fpgaTimerStop(timer);

    /* Make sure that the Snapshot mode is disabled */
    fpgaTimerDisableSnapshot(timer);

    if (timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2)
    {
        regAdrs = (ULONG)FPGA_SET0_TMR0_INTERVAL;
    }
    else
    {
        regAdrs = (ULONG)FPGA_SET1_TMR0_INTERVAL;
        timer -= IOFPGA_TIMER1_0;
    }


    countAddr = (ULONG)(regAdrs - timer * 4) + 3;
    countByte = (UINT8) (count & 0xff);
    sysOutByte(countAddr, countByte);

    countAddr = (ULONG)(regAdrs - timer * 4) + 2;
    countByte = (UINT8) ((count & 0xff00) >> 8);
    sysOutByte(countAddr, countByte);

    countAddr = (ULONG)(regAdrs - timer * 4) + 1;
    countByte = (UINT8) ((count & 0xff0000) >> 16);
    sysOutByte(countAddr, countByte);

    countAddr = (ULONG)(regAdrs - timer * 4);
    countByte = (UINT8) ((count & 0xff000000) >> 24);
    sysOutByte(countAddr, countByte);

    
    return BSP_OK;
}


/*******************************************************************************
* fpgaTimerRead - Read the FPGA timer
*
* DESCRIPTION: Reading the FPGA timer will clear the interrupt in the interrupt
*              status register
*
* INPUT:
*
* RETURN:
*
*/
BSP_STATUS fpgaTimerRead(IOFPGA_TIMER timer, unsigned int *count)
{
    unsigned int regAdrs;

    ULONG countAddr;

    
    if (timer <= IOFPGA_TIMER_START && timer >= IOFPGA_TIMER_END)
        return BSP_INVALID_PARAM;

    if (((timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2) && (sysProcId != CPU_ID_0)) ||
        ((timer >= IOFPGA_TIMER1_0 && timer <= IOFPGA_TIMER1_2) && (sysProcId != CPU_ID_1)))
        return BSP_INVALID_PARAM;

    /* set 0 */
    if (timer >= IOFPGA_TIMER0_0 && timer <= IOFPGA_TIMER0_2)
    {
        regAdrs = (ULONG)FPGA_SET0_TMR0_INTERVAL;
            /* Latch the counter value by enabling Snapshot mode */
        fpgaTimerEnableSnapshot (timer);


	*count = 0;	
	countAddr = (ULONG)(regAdrs - timer * 4) + 3;
	*count |= sysInByte(countAddr);

	countAddr = (ULONG)(regAdrs - timer * 4) + 2;
	*count |= (sysInByte(countAddr) << 8);

	countAddr = (ULONG)(regAdrs - timer * 4) + 1;
	*count |= (sysInByte(countAddr) << 16);

	countAddr = (ULONG)(regAdrs - timer * 4);
	*count |= (sysInByte(countAddr) << 24);
	
        fpgaTimerIntClear (timer );
        fpgaTimerDisableSnapshot (timer); 
    }
    else
    {
	/* set 1 */
        regAdrs = (ULONG)FPGA_SET1_TMR0_INTERVAL;
        timer -= IOFPGA_TIMER1_0;

        /* Latch the counter value by enabling Snapshot mode */
        fpgaTimerEnableSnapshot (timer + IOFPGA_TIMER1_0);
	/*     *count  = sysInLong((ULONG)(regAdrs - timer*4)); */
		*count = 0;	
	countAddr = (ULONG)(regAdrs - timer * 4) + 3;
	*count |= sysInByte(countAddr);

	countAddr = (ULONG)(regAdrs - timer * 4) + 2;
	*count |= (sysInByte(countAddr) << 8);

	countAddr = (ULONG)(regAdrs - timer * 4) + 1;
	*count |= (sysInByte(countAddr) << 16);

	countAddr = (ULONG)(regAdrs - timer * 4);
	*count |= (sysInByte(countAddr) << 24);
	
        fpgaTimerIntClear (timer + IOFPGA_TIMER1_0);
        fpgaTimerDisableSnapshot (timer + IOFPGA_TIMER1_0);
    }

    return BSP_OK;
}

int getTimer (IOFPGA_TIMER timer)
{
    unsigned int count = 0;
    fpgaTimerRead(timer, &count);
    return count;
    
}