diffdiofpga.c

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

    intUnlock (lock);
    return (OK);
    }


/***************************************************************************
*
* difDioIntConnect - connect a routine to the Differential I/O (Diff I/O) interrupt
*
* This routine specifies the interrupt serivce routine to be called at each
* interrupt for the corresponding bit in the status register.
*
* RETURNS: OK or ERROR if the passed ISR is NULL or if attempting to connect ISR to uninitialized difDio lines
*
* SEE ALSO: intConnect(), difDioIntEnable()
*/

STATUS difDioIntConnect
    (
    UINT32  difMask,      /* interrupt mask to attach */
    FUNCPTR difRoutine,   /* routine to be called */
    int     arg           /* parameter to be passed to routine */
    )
    {
    int lock;
    volatile int bitcount, checkbit;
    
        /* ensure passed routine is not NULL */
    if(NULL == (VOIDFUNCPTR) difRoutine)
      {
          logMsg("ERROR: attempting to attach null as interrupt service routine!\n",0,0,0,0,0,0);
          return ERROR;
      }
    /* check if attempting to connect ISR to uninitialized difDio line */
    if(0 != (difMask & (~ddioEnabled)))
      {
        logMsg("ERROR: attempting to connect ISR to uninitialized difDio lines!\n",0,0,0,0,0,0);
	return ERROR;
      }
    difMask &= ddioEnabled;
    for (bitcount = 0; bitcount < DIF_LINES; bitcount++)
        {
        checkbit = (difMask & (1 << bitcount)) ? 1 : 0;

        if (checkbit == 1)
            {
            /* initialize the new handler */            
            lock = intLock ();

            intConnect ((void *)(FPGA_DIFFIO_0_INT_SRC + bitcount), (VOIDFUNCPTR) difRoutine, arg);

            intUnlock (lock);
            }
        }
        
    return (OK);
    }

/***************************************************************************
*
* difDioWrite - Write to the Differential Output Data lines
*
* This routine writes 8-bit data passed in as <value> out to the Diff I/O lines
*
* RETURNS: OK.
*
* SEE ALSO: difDioRead()
*/

STATUS difDioWrite 
    (
    UINT8 diffLines       /* write 1 to the specified Diff I/O data lines */ 
    )
    {
    STATUS stat = ERROR;
    UINT8 regValue;

    if (ddioEnabled > 0) /* are any lines are enabled? */
      {
      regValue = sysInByte ((UINT32)FPGA_DIFFDIO_DOUT);
      /* Write value to the DDIO lines */
      sysOutByte((UINT32)FPGA_DIFFDIO_DOUT, (diffLines & ddioEnabled)|(regValue & ~ddioEnabled));
      stat = OK;
      }

    return stat;
    } 

/***************************************************************************
*
* difDioRead - Read the 8-bit Data from Diff I/O and store it in RAM
*
* This routine reads the Diff I/O DATA IN register and stores the 8-bit value at the 
* location referenced by the input parameter.
*
* RETURNS: OK.
*
* SEE ALSO: difDioWrite()
*/

STATUS difDioRead 
    (
    UINT8 *pValue  /* pointer to returned data */
    )
    {
    STATUS stat = ERROR;

    if (ddioEnabled > 0)
        {
        *pValue = sysInByte ((UINT32)FPGA_DIFFDIO_DIN);
        stat = OK;
	}

    return stat;    
    }

/***************************************************************************
*
* difDioIntEdgeSet - sets the interrupt triggering edge of specified input lines
*
* This routine sets the edge which will trigger an interrupt for each
* differential input line whose bit is set in the mask.
* This function doesn't allow users to change the triggering edge of diffio lines which have interrupts enabled.
* The edge flag (difEdge) can be either RISING or FALLING (see dio_dy4.h).
*
* RETURNS: OK if successful, ERROR if difEdge parameter is invalid or if attempting to change triggering edge to 
* uninitialized difDio lines or the passed difMask contains diffio lines which have interrupts enabled
*
*
*/

STATUS difDioIntEdgeSet(UINT8 difMask, BOOL difEdge)
    {
    volatile  UINT8 readReg;
    int lock;
    UINT32 diffioIntEnableMask;
    /* check if attempting to change triggering edge to uninitialized difDio lines*/
    if(0 != (difMask & (~ddioEnabled)))
      {
        logMsg("ERROR: attempting to change triggering edge to uninitialized difDio lines\n",0,0,0,0,0,0);
	return ERROR;
      }

    /* check if attempting to set triggering edge of diffio lines which interrupts are enabled */

    /* get current diffio  int enable mask */
    diffioIntEnableMask = sysInByte((UINT32)FPGA_DIFFDIO_INTENBL) ;

    /* check which of these DIFFIO interrupts enabled to this CPU */
    diffioIntEnableMask &= getDifDioIntMask();

    /* Make sure not to set triggering edge of DIFFIO bits which have interrupts enabled   */
    if (0 != (difMask & diffioIntEnableMask))
      {
        logMsg("ERROR: attempting to change direction of DIFFIO bits which have interrupts enabled!\n",0,0,0,0,0,0);
	return ERROR;
      }
    lock = intLock();

    switch (difEdge)
        {
        case RISING: /* Interrupt on rising edge - set 1's in register bits */
            readReg =  sysInByte ((UINT32)FPGA_DIFFDIO_EDGE);
            readReg |= (difMask & ddioEnabled);
            sysOutByte ((UINT32)FPGA_DIFFDIO_EDGE, (UINT8)readReg);
            break;

        case FALLING: /* Interrupt on falling edge - set register bits to 0 */
            readReg =  sysInByte ((UINT32)FPGA_DIFFDIO_EDGE);
            readReg &= ~(difMask & ddioEnabled);
            sysOutByte ((UINT32)FPGA_DIFFDIO_EDGE, readReg);
            break;

        default :
            intUnlock (lock);
            return (ERROR); /* invalid difEdge parameter */
        }

    /* Clear interrupts genrated as a result of changing the triggering edge */
    /* Make sure to enable diffio interrupts from the DIFFIO_INT_ENBL register to get visibility to
       the DIDDIO_INT_STAT register. Note that interrupts are still masked in the CPU mask level */

    sysOutByte((UINT32)FPGA_DIFFDIO_INTENBL, difMask);

    /* Clear interrupts in the STAT register */
    sysOutByte((UINT32)FPGA_DIFFDIO_INTSTAT, difMask);
    
    intUnlock (lock);
    return (OK);
    }

/*******************************************************************************
* fpgaDifDioIntClear - Clear FPGA diffio INT
*
* DESCRIPTION: Clear the FPGA diffio INT by clearing the FPGA_DIFFDIO_INTSTAT register bit
*
* INPUT:
*
* RETURN:
*
*/
void fpgaDifDioIntClear(int diffio)
{

    sysOutByte((ULONG)FPGA_DIFFDIO_INTSTAT, 1 << diffio);

}



/*******************************************************************************
 * int getDifDioIntMask(void)
 *
 * Get the DIFFDIO (IOFPGA 0 - 7) interrupt mask
 *
 */
unsigned int getDifDioIntMask(void)
{
   UINT32 mask;
   if(sysProcId==0)
       mask = sysInByte((UINT32)FPGA_CPU0_DIFFDIO_INTMSK);
   else
       mask = sysInByte((UINT32)FPGA_CPU1_DIFFDIO_INTMSK);
   return mask;
}


/*******************************************************************************
* dioDefaultIsr - DIFFIO default ISR
*
* DESCRIPTION:
*
* INPUT:
*
* RETURN:
*
* NOMANUAL
*/
LOCAL void difDioDefaultIsr(int diffio)
{
  logMsg("No interrupt handler attached to diffio %d\n",diffio,2,3,4,5,6) ;
}


#ifdef INCLUDE_SHOW_ROUTINES

void difDioShow(void)
    {
    printf("\nInterrupt Registers:\n");
    printf("CPU0 FPGA DIFFIO Interrupt Source Register\t0x%X\n",sysInByte ((UINT32)FPGA_CPU0_DIFFDIO_INTSRC));
    printf("CPU0 FPGA DIFFIO Interrupt Mask Register\t0x%X\n",sysInByte ((UINT32)FPGA_CPU0_DIFFDIO_INTMSK));

    printf("CPU1 FPGA DIFFIO Interrupt Source Register\t0x%X\n",sysInByte ((UINT32)FPGA_CPU1_DIFFDIO_INTSRC ));
    printf("CPU1 FPGA DIFFIO Interrupt Mask Register\t0x%X\n",sysInByte ((UINT32)FPGA_CPU1_DIFFDIO_INTMSK));

    printf("\nDifferential IO Registers:\n");
    printf("[0x252] Interrupt Enable Register\t0x%X\n", sysInByte ((UINT32)FPGA_DIFFDIO_INTENBL));
    printf("[0x262] Interrupt Status Register\t0x%X\n", sysInByte ((UINT32)FPGA_DIFFDIO_INTSTAT));

    printf("[0x103] DIFFIO Read Data Register \t0x%X\n", sysInByte ((UINT32)FPGA_DIFFDIO_DIN));
    printf("[0x104] DIFFIO Write Data Register\t0x%X\n", sysInByte ((UINT32) FPGA_DIFFDIO_DOUT));
    printf("[0x202] DIFFIO Interrupt Edge Register\t0x%X\n", sysInByte ((UINT32)FPGA_DIFFDIO_EDGE));
    printf("[0x101] DIFFIO CTRL Register\t\t0x%X\n", sysInByte ((UINT32)FPGA_DIFFDIO_CTRL));
    printf("[0x100] DIFFIO ROUTE Register\t\t0x%X\n", sysInByte ((UINT32)FPGA_DIFFDIO_ROUTE));
    }

#endif /* INCLUDE_SHOW_ROUTINES */

#ifdef __cplusplus
}
#endif