z85230drv.c

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

  {
  char* pCh=NULL;
 
  /* reset the global error */
  gZ85230Errno = 0 ;

  /* Verify that the driver has been installed,
   * can not create a valid device for a driver that
   * does not exist.
   */
  if( gZ85230DrvNum == ERROR )
    {
    errno = S_ioLib_NO_DRIVER ;
    gZ85230Errno = errno ;
    return ERROR ;
    }

  /* find an existing device, if a device with this name already 
   * exists, the string pointed to by pCh != 0
   */ 
  iosDevFind( devName, &pCh );  

  /* Validate the input parameters */
  if(   ( devName == NULL )
     || ( strlen(devName) < 1 )
     || ( strlen(pCh) == 0 )
     || (  (channel != Z85230_CHANNEL_A)
         &&(channel != Z85230_CHANNEL_B)
        )
    )
    {  
    errno = EINVAL ;
    gZ85230Errno = errno ;
    return ERROR;
    }

  /* Verify a device has not already been created for this channel
   * if it has, the the channel.name will not be null. Only one device
   * allowed per channel
   */
  if ( gZ85230Channels[ channel ]->name != NULL )
    {  
    errno = EINVAL ;
    gZ85230Errno = errno ;
    return ERROR;
    }

  /*
   * Verify no other device is using the same DMA channel  
   */
  switch ( channel )
    { 
    case Z85230_CHANNEL_A:
      /* lock out requests to the ESCC Rx, Tx DMA channel via gt64260 driver */
      /* semTake( gt.dmaQueueSem[ SCC_RXA_DMA_CHAN ], WAIT_FOREVER ); aak ***/
      /* semTake( gt.dmaQueueSem[ SCC_TXA_DMA_CHAN ], WAIT_FOREVER ); aak ***/
  	  
      /* fall through to channel B case */
    case Z85230_CHANNEL_B:
      {
      int result;
      Z85230_DEV * device = &(gZ85230Devices[ channel ]);
      int len = 0 ;
 
      /* device name */
      len = strlen( devName );
      device->channel.name = (char *)malloc( len + 1 );
      if ( device->channel.name == NULL )
	{
	/* out of memory! */

	/* errno set by vxworks */
	return ERROR;
	}
      memcpy( device->channel.name, devName, len + 1 );

      /* device number */
      device->channel.channel = channel;
      result = iosDevAdd( &(device->devHdr), devName, 
			gZ85230DrvNum );

      if ( result == OK )
	{
	/* TODO: initialize z85230Channel, z85230Protocol, 
	   z85230ProtocolHDLC */
	}

      return result;
      }

    default:
      return ERROR;
    }
  }

/***************************************************************************
 * z85230DevRemove - "disconnect" a channel from the file system
 *
 * RETURNS
 * OK: success
 * ERROR: failure
 */
STATUS z85230DevRemove( char * devName ) 
  {
  /* find correct channel */
  int channelIdx = 0;

  if ( devName == NULL )
    {
    /* bad pointer */
    errno = S_ioLib_NO_FILENAME ;
    return ERROR;
    }

  for ( channelIdx = 0; channelIdx < Z85230_NUM_CHANNELS; channelIdx++ )
    {
    if ( !strcmp( devName, gZ85230Channels[ channelIdx ]->name ) )
      {
      break;
      }
    }

  if ( channelIdx == Z85230_NUM_CHANNELS )
    {
    /* channel not found */
    /* TODO: set errno */
    return ERROR;
    }

  /* remove channel */
  iosDevDelete( &( gZ85230Devices[ channelIdx ].devHdr ) );

  /* channel name */
  free( gZ85230Channels[ channelIdx ]->name );
  gZ85230Channels[ channelIdx ]->name = NULL;

  /* free DMA semaphores *** commented aak *
  if ( channelIdx == Z85230_CHANNEL_A )
    {
    semGive( gt.dmaQueueSem[ SCC_RXA_DMA_CHAN ] );
    semGive( gt.dmaQueueSem[ SCC_TXA_DMA_CHAN ] );
    }
   */
  return OK;
  }

#ifdef VME_181
/***************************************************************************
 * z85230DrvDmaRxAInt - DMA interrupt handler for the Rx channel
 *
 */
LOCAL void z85230DrvDmaRxAInt( int dma_int )
  {
  gZ85230DmaRxAIntCount++;
  /* Z85230_LOG( "RxA DMA Interrupt" ); */

  (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.rxDmaInt)(
    gZ85230Channels[ Z85230_CHANNEL_A ] );
  
  gtDmaIntAck(dma_int);
  }

/***************************************************************************
 * z85230DrvDmaTxAInt - DMA interrupt handler for the Tx channel
 *
 */
LOCAL void z85230DrvDmaTxAInt( int dma_int )
  {
  gZ85230DmaTxAIntCount++;
  /* Z85230_LOG( "TxA DMA Intrpt" ); */
  
  (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.txDmaInt)(
    gZ85230Channels[ Z85230_CHANNEL_A ] );

  gtDmaIntAck(dma_int);
  }

/***************************************************************************
 * z85230DrvDmaRxBInt - DMA interrupt handler for the Rx channel
 *
 */
LOCAL void z85230DrvDmaRxBInt( int dma_int )
  {
  gZ85230DmaRxBIntCount++;
  /* Z85230_LOG( "RxB DMA Intrpt" ); */

  (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.rxDmaInt)(
    gZ85230Channels[ Z85230_CHANNEL_B ] );
  
  gtDmaIntAck(dma_int);
  }

/***************************************************************************
 * z85230DrvDmaTxBInt - DMA interrupt handler for the Tx channel
 *
 */
LOCAL void z85230DrvDmaTxBInt( int dma_int )
  {
  gZ85230DmaTxBIntCount++;
  /* Z85230_LOG( "TxB DMA Intrpt/n" ); */
  
  (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.txDmaInt)(
    gZ85230Channels[ Z85230_CHANNEL_B ] );
  gtDmaIntAck(dma_int);
  }

#endif /* VME_181 */

/***************************************************************************
 * z85230DrvInt - interrupt handler
 *
 */
LOCAL void z85230DrvInt( int dummy )
  {
  volatile unsigned char * crA = gZ85230Channels[ Z85230_CHANNEL_A ]->hw.cr;
  volatile unsigned char * crB = gZ85230Channels[ Z85230_CHANNEL_B ]->hw.cr;
#ifdef VME_181
  volatile unsigned char intStatus = 0;
#else
  unsigned int intStatus;
  unsigned int intStat;
#endif
/*
  char * intNames[] = {
    "TxA", "TxB",
    "RxA", "RxB",    
    "ExA", "ExB",
    "RxA FPGA", "RxB FPGA",    
    "TxA FPGA", "TxB FPGA"    
  };
*/
 /*
  * Check FPGA DMA interrupt first
  */
#ifdef VME_181
  intStatus = sysInByte ( (UINT32)FPGA_SCC_INT_STAT); 

  if (intStatus & 0x40) /* Ch A RX FPGA interrupt */
  {  gZ85230RXAFpgaCount++;

	/* Z85230_LOG( intNames[ 6 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.rxFpgaInt)(
      gZ85230Channels[ Z85230_CHANNEL_A ]);
  }

  if ( (intStatus & 0x04) != 0 ) /* Ch B RX FPGA interrupt */
  {  gZ85230RXBFpgaCount++;
    /* Z85230_LOG( intNames[ 7 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.rxFpgaInt)(
      gZ85230Channels[ Z85230_CHANNEL_B ]);
  }

  if (intStatus & 0x10) /* Ch A TX FPGA interrupt */
  {  /* gZ85230TXAFpgaCount++; */

	/* Z85230_LOG( intNames[ 8 ] ); */
	if ((gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.txFpgaInt)) 
    (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.txFpgaInt)(
      gZ85230Channels[ Z85230_CHANNEL_A ]);
  }

  if ( (intStatus & 0x01) != 0 ) /* Ch B TX FPGA interrupt */
  {  /* gZ85230TXBFpgaCount++; */
    /* Z85230_LOG( intNames[ 9 ] );  */
	if ((gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.txFpgaInt)) 
    (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.txFpgaInt)(
      gZ85230Channels[ Z85230_CHANNEL_B ]);
  }

#else
  intStatus = intStat = sysInLong ( (UINT32)FPGA_SCC_INT_STAT); 
  while (1)
  {
    if (intStat & DRI_RXA_INT_STAT)
    {
      gZ85230RXAFpgaCount++;
      (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.rxFpgaInt)(
        gZ85230Channels[ Z85230_CHANNEL_A ]);
    }
    else if (intStat & DRI_RXB_INT_STAT)
    {
      gZ85230RXBFpgaCount++;
      (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.rxFpgaInt)(
        gZ85230Channels[ Z85230_CHANNEL_B ]);
    }
    else if (intStat & DRI_TXA_INT_STAT)
    {
      gZ85230TXAFpgaCount++;
      (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.txFpgaInt)(
        gZ85230Channels[ Z85230_CHANNEL_A ]);
    }
    else if (intStat & DRI_TXB_INT_STAT)
    {
      gZ85230TXBFpgaCount++;
      (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.txFpgaInt)(
        gZ85230Channels[ Z85230_CHANNEL_B ]);
    }
    else
      break;

    intStat = sysInLong ( (UINT32)FPGA_SCC_INT_STAT); 
  }

  return;

#endif /* VME_181 */

/*
 * Now check Zilog interrupts:
 */

  REG_8530_READ( crA, &intStatus );
  REG_8530_WRITE( crA,  SCC_WR0_SEL_WR3 );
  REG_8530_READ( crA, &intStatus );

  if ( intStatus == 0 )
    {
    return;
    }

  gZ85230IntCount++;

  if ( (intStatus & SCC_RR3_A_TX_IP) != 0 )
    {
    gZ85230TXAIntCount++;
    /* Z85230_LOG( intNames[ 0 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.txInt)(
      gZ85230Channels[ Z85230_CHANNEL_A ], intStatus );
    }

  if ( (intStatus & SCC_RR3_B_TX_IP) != 0 )
    {
    gZ85230TXBIntCount++;
    /* Z85230_LOG( intNames[ 1 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.txInt)(
      gZ85230Channels[ Z85230_CHANNEL_B ], intStatus );
    }

  if ( (intStatus & SCC_RR3_A_RX_IP) != 0 )
    {
    gZ85230RXAIntCount++;
    /* Z85230_LOG( intNames[ 2 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.rxInt)(
      gZ85230Channels[ Z85230_CHANNEL_A ], intStatus );
    }

  if ( (intStatus & SCC_RR3_B_RX_IP) != 0 )
    {
    gZ85230RXBIntCount++;
    /* Z85230_LOG( intNames[ 3 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.rxInt)(
      gZ85230Channels[ Z85230_CHANNEL_B ], intStatus );
    }

  if ( (intStatus & SCC_RR3_A_EXT_IP) != 0 )
    {
    gZ85230EXAIntCount++;
    /* Z85230_LOG( intNames[ 4 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_A ]->protocol.exInt)(
      gZ85230Channels[ Z85230_CHANNEL_A ], intStatus );
    }

  if ( (intStatus & SCC_RR3_B_EXT_IP) != 0 )
    {
    gZ85230EXBIntCount++;
    /* Z85230_LOG( intNames[ 5 ] ); */
    (*gZ85230Channels[ Z85230_CHANNEL_B ]->protocol.exInt)(
      gZ85230Channels[ Z85230_CHANNEL_B ], intStatus );
    }

  /* reset any error condition */
  REG_8530_WRITE( crA, SCC_WR0_ERR_RST );
  REG_8530_WRITE( crB, SCC_WR0_ERR_RST );
  
  /* Reset the interrupt in the Z8530 */
  REG_8530_WRITE( crA, SCC_WR0_RST_HI_IUS );

  /* Dummy read to ensure accomplishment of the prev. command */
  REG_8530_READ( crA, &intStatus );
  }


/*** z85230Drv.c - end of file ***/