pci.h

PCI总线在DOS操作系统下的驱动程序源代码

#define DEVICE_COUNT_COMPATIBLE	4
#define DEVICE_COUNT_IRQ	2
#define DEVICE_COUNT_DMA	2
#define DEVICE_COUNT_RESOURCE	12

#define PCI_ANY_ID (~0L)

#define PCIBIOS_MIN_IO		0x1000
#define PCIBIOS_MIN_MEM		0x10000000UL

#define pci_present pcibios_present

#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)

#define pci_bus_b(n) list_entry(n, struct pci_bus, node)

#define pci_for_each_dev(dev) \
	for(dev = pci_dev_g(pci_devices.next); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.next))

#define pci_for_each_dev_reverse(dev) \
	for(dev = pci_dev_g(pci_devices.prev); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.prev))

#define pci_for_each_bus(bus) \
for(bus = pci_bus_b(pci_root_buses.next); bus != pci_bus_b(&pci_root_buses); bus = pci_bus_b(bus->node.next))

struct resource {
	const char *name;
	unsigned long start, end;
	unsigned long flags;
	struct resource *parent, *sibling, *child;
};

#define pci_resource_start(dev,bar)   ((dev)->resource[(bar)].start)
#define pci_resource_end(dev,bar)     ((dev)->resource[(bar)].end)
#define pci_resource_flags(dev,bar)   ((dev)->resource[(bar)].flags)
#define pci_resource_len(dev,bar) \
	((pci_resource_start((dev),(bar)) == 0 &&	\
	  pci_resource_end((dev),(bar)) ==		\
	  pci_resource_start((dev),(bar))) ? 0 :	\
	  						\
	 (pci_resource_end((dev),(bar)) -		\
	  pci_resource_start((dev),(bar)) + 1))


/*
 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
 */
struct pci_dev {
	struct list_head global_list;	/* node in list of all PCI devices */
	struct list_head bus_list;	/* node in per-bus list */
	struct pci_bus	*bus;		/* bus this device is on */
	struct pci_bus	*subordinate;	/* bus this device bridges to */

	void		*sysdata;	/* hook for sys-specific extension */
	
	unsigned long	devfn;		/* encoded device & function index */
	unsigned short	vendor;
	unsigned short	device;
	unsigned short	subsystem_vendor;
	unsigned short	subsystem_device;
	unsigned long	class;		/* 3 bytes: (base,sub,prog-if) */
	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
	u8		rom_base_reg;	/* which config register controls the ROM */

	struct pci_driver *driver;	/* which driver has allocated this device */
	void		*driver_data;	/* data private to the driver */
	u64		dma_mask;	/* Mask of the bits of bus address this
					   device implements.  Normally this is
					   0xffffffff.  You only need to change
					   this if your device has broken DMA
					   or supports 64-bit transfers.  */

	u32             current_state;  /* Current operating state. In ACPI-speak,
					   this is D0-D3, D0 being fully functional,
					   and D3 being off. */

	/* device is compatible with these IDs */
	unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
	unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];

	/*
	 * Instead of touching interrupt line and base address registers
	 * directly, use the values stored here. They might be different!
	 */
	unsigned long	irq;
	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
	struct resource dma_resource[DEVICE_COUNT_DMA];
	struct resource irq_resource[DEVICE_COUNT_IRQ];

	char		name[80];	/* device name */
	char		slot_name[8];	/* slot name */
	long		active;		/* ISAPnP: device is active */
	long		ro;		/* ISAPnP: read only */
	unsigned short	regs;		/* ISAPnP: supported registers */

	long (*prepare)(struct pci_dev *dev);	/* ISAPnP hooks */
	long (*activate)(struct pci_dev *dev);
	long (*deactivate)(struct pci_dev *dev);
};

/*
 *  For PCI devices, the region numbers are assigned this way:
 *
 *	0-5	standard PCI regions
 *	6	expansion ROM
 *	7-10	bridges: address space assigned to buses behind the bridge
 */

#define PCI_ROM_RESOURCE 6
#define PCI_BRIDGE_RESOURCES 7
#define PCI_NUM_RESOURCES 11
  
#define PCI_REGION_FLAG_MASK 0x0f	/* These bits of resource flags tell us the PCI region flags */

struct pci_bus {
	struct list_head node;		/* node in list of buses */
	struct pci_bus	*parent;	/* parent bus this bridge is on */
	struct list_head children;	/* list of child buses */
	struct list_head devices;	/* list of devices on this bus */
	struct pci_dev	*self;		/* bridge device as seen by parent */
	struct resource	*resource[4];	/* address space routed to this bus */

	struct pci_ops	*ops;		/* configuration access functions */
	void		*sysdata;	/* hook for sys-specific extension */
	
	unsigned char	number;		/* bus number */
	unsigned char	primary;	/* number of primary bridge */
	unsigned char	secondary;	/* number of secondary bridge */
	unsigned char	subordinate;	/* max number of subordinate buses */

	char		name[48];
	unsigned short	vendor;
	unsigned short	device;
	unsigned long	serial;		/* serial number */
	unsigned char	pnpver;		/* Plug & Play version */
	unsigned char	productver;	/* product version */
	unsigned char	checksum;	/* if zero - checksum passed */
	unsigned char	pad1;
};
 
extern struct list_head pci_root_buses;	/* list of all known PCI buses */
extern struct list_head pci_devices;	/* list of all devices */

/* Low-level architecture-dependent routines */

struct pci_ops {
	long (*read_byte)(struct pci_dev *, long, u8 *);
	long (*read_word)(struct pci_dev *, long , u16 *);
	long (*read_dword)(struct pci_dev *, long , u32 *);
	long (*write_byte)(struct pci_dev *, long , u8 );
	long (*write_word)(struct pci_dev *, long , u16 );
	long (*write_dword)(struct pci_dev *, long , u32 );
};

struct pci_device_id {
	unsigned long vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
	unsigned long subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
	unsigned long class, class_mask;		/* (class,subclass,prog-if) triplet */
	unsigned long driver_data;		/* Data private to the driver */
};

struct pci_driver {
	struct list_head node;
	char *name;
	const struct pci_device_id *id_table;	/* NULL if wants all devices */
	long  (*probe)  (struct pci_dev far * dev, const struct pci_device_id far * id);/* New device inserted */
	void (*remove) (struct pci_dev far * dev);	/* Device removed (NULL if not a hot-plug capable driver) */
	long  (*save_state) (struct pci_dev far * dev, u32 state);    /* Save Device Context */

	#ifdef	CONFIG_PM

		long  (*suspend)(struct pci_dev far * dev, u32 state);	/* Device suspended */
		long  (*resume) (struct pci_dev far * dev);	                /* Device woken up */

	#endif

	long  (*enable_wake) (struct pci_dev far * dev, u32 state, long enable);   /* Enable wake event */
};

struct pci_fixup {
	long pass;
	u16 vendor, device;			/* You can use PCI_ANY_ID here of course */
	void (*hook)(struct pci_dev *dev);
};

struct irq_info {
	u8 bus, devfn;			/* Bus, device and function */
	struct {
		u8 link;		/* IRQ line ID, chipset dependent, 0=not routed */
		u16 bitmap;		/* Available IRQs */
	} irq[4]; 
	u8 slot;			/* Slot number, 0=onboard */
	u8 rfu;
};

struct irq_routing_options {
	u16 size;
	struct irq_info far * table;
	u16 segment;
};

struct irq_routing_table {
	u32 signature;			/* PIRQ_SIGNATURE should be here */
	u16 version;			/* PIRQ_VERSION */
	u16 size;			/* Table size in bytes */
	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */
	u16 exclusive_irqs;		/* IRQs devoted exclusively to PCI usage */
	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of interrupt router */
	u32 miniport_data;		/* Crap */
	u8 rfu[11];
	u8 checksum;			/* Modulo 256 checksum must give zero */
	struct irq_info slots[0];
};

struct irq_router {
	char *name;
	u16 vendor, device;
	long (*get)(struct pci_dev *router, struct pci_dev *dev, long pirq);
	long (*set)(struct pci_dev *router, struct pci_dev *dev, long pirq, long new);
};

extern struct pci_fixup pcibios_fixups[];

#define PCI_FIXUP_HEADER	1		/* Called immediately after reading configuration header */
#define PCI_FIXUP_FINAL		2		/* Final phase of device fixups */

/*
 *  Wrappers for all PCI configuration access functions.  They just check
 *  alignment, do locking and call the low-level functions pointed to
 *  by pci_dev->ops.
 */

#define PCI_byte_BAD 0
#define PCI_word_BAD (pos & 1)
#define PCI_dword_BAD (pos & 3)

long pci_read_config_byte (struct pci_dev *dev, long pos, u8 *  value); 
long pci_read_config_word (struct pci_dev *dev, long pos, u16 *  value); 
long pci_read_config_dword (struct pci_dev *dev, long pos, u32 *  value); 
long pci_write_config_byte (struct pci_dev *dev, long pos, u8 value); 
long pci_write_config_word (struct pci_dev *dev, long pos, u16 value); 						
long pci_write_config_dword (struct pci_dev *dev, long pos, u32 value); 

extern unsigned short pci_probe;
extern int pci_bios_present;

#define PCI_PROBE_BIOS  1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
#define PCI_NO_SORT	  0x0100
#define PCI_BIOS_SORT 0x0200
#define PCI_NO_CHECKS 0x0400
#define PCI_ASSIGN_ROMS		0x1000
#define PCI_BIOS_IRQ_SCAN	0x2000
#define PCI_ASSIGN_ALL_BUSSES	0x4000

#define PCI_FUNCTION_ID 0xB1
#define PCI_BIOS_PRESENT 0x01
#define FIND_PCI_DEVICE 0x02
#define FIND_PCI_CLASS_CODE 0x03
#define GENERATE_SPECIAL_CYCLE 0x06
#define READ_CONFIG_BYTE 0x08
#define READ_CONFIG_WORD 0x09
#define READ_CONFIG_DWORD 0x0A
#define WRITE_CONFIG_BYTE 0x0B
#define WRITE_CONFIG_WORD 0x0C
#define WRITE_CONFIG_DWORD 0x0D
#define GET_IRQ_ROUTING_OPTIONS 0x0E
#define SET_PCI_IRQ 0x0F

/* PCI BIOS hardware mechanism flags */
#define PCIBIOS_HW_TYPE1		0x01
#define PCIBIOS_HW_TYPE2		0x02
#define PCIBIOS_HW_TYPE1_SPEC		0x10
#define PCIBIOS_HW_TYPE2_SPEC		0x20

#define SUCCESSFUL 0x00
#define FUNC_NOT_SUPPORTED 0x81
#define BAD_VENDOR_ID 0x83
#define DEVICE_NOT_FOUND 0x86
#define BAD_REGISTER_NUMBER 0x87
#define SET_FAILED 0x88
#define BUFFER_TOO_SMALL 0x89

#define PCIBIOS_SIGNATURE 0x4350

#define IO_SPACE_LIMIT 0xffff