pll_50.inc

来自「sdram 控制器的verilog 实现」· INC 代码 · 共 26 行

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--and other software and tools, and its AMPP partner logic 
--functions, and any output files from any of the foregoing 
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FUNCTION pll_50 
(
	inclk0
)

RETURNS (
	c0,
	e0,
	locked
);