📄 pll_50_waveforms.html
字号:
<html>
<head>
<title>Sample Waveforms for pll_50.v </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file pll_50.v </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll_50.v. The design pll_50.v has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 50000 ps. Output port LOCKED will go high when the PLL locks to the input clock. </P>
<CENTER><img src=pll_50_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
</body>
</html>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -