top.tan.summary

sdram 控制器的verilog 实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 13.464 ns
From           : key_rst_n
To             : sdram_top:inst|refresh:U2|refresh_cnt[3]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.287 ns
From           : user_interface:inst3|rom256:rom256_inst|altsyncram:altsyncram_component|altsyncram_2361:auto_generated|altsyncram_fk72:altsyncram1|ram_block3a0~porta_address_reg7
To             : sdram_data[11]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.790 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'pll_50:inst1|altpll:altpll_component|_clk0'
Slack          : 1.195 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[1]
To             : sdram_top:inst|refresh:U2|refresh_cnt[3]
From Clock     : clk
To Clock       : pll_50:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : 45.930 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : 245.70 MHz ( period = 4.070 ns )
From           : reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[1]
To             : reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 64.09 MHz ( period = 15.604 ns )
From           : user_interface:inst3|ram512:ram512_inst|altsyncram:altsyncram_component|altsyncram_0qe1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'pll_50:inst1|altpll:altpll_component|_clk0'
Slack          : 0.822 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : user_interface:inst3|read_req
To             : user_interface:inst3|read_req
From Clock     : pll_50:inst1|altpll:altpll_component|_clk0
To Clock       : pll_50:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : 1.323 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[4]
To             : reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[4]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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