patoseri.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity patoser is
port(
     reset,rxclk,rclk16x:in std_logic;
     ncs,nwr,rxrdyn:in std_logic;
     addr:in std_logic_vector(2 downto 0);
     datain:in std_logic_vector(1 downto 0);
     datainpa:in std_logic_vector(7 downto 0);
     ds2172dataout:out std_logic;    
     datard:out std_logic; 
     ds2172rclk:out std_logic
    );
end;

architecture behavioral of patoser is

signal databit:std_logic_vector(1 downto 0);
signal i,j:std_logic_vector(3 downto 0);
signal counter:std_logic_vector(2 downto 0);
signal datardbuf,flag:std_logic;
signal sdataoutbuf:std_logic;
signal counterrx:std_logic_vector(3 downto 0);
signal counterbuf:std_logic_vector(1 downto 0);
signal rxclkbuf:std_logic;
signal datainpabuf:std_logic_vector(7 downto 0);
signal latchclk:std_logic;

begin
 rxclkbuf<=not rxclk;
 latchclk<= (not rxrdyn) and (not datardbuf) and  rxclk;

 process(latchclk,datainpa)
  begin
   if latchclk'event and latchclk='1'then
      datainpabuf<=datainpa;
   end if;
 end process; 

 process(reset,ncs,nwr,addr,datain)
   begin
     if reset='1'then
       databit<="11";
       --databit<="01";         
     elsif nwr'event and nwr='1'then
       if ncs='0' and addr="011"then   
         databit<=datain;
       end if;
     end if;
 end process;

 process(databit,rxrdyn)
  begin
    if databit="00" then
      i<="0110"; 
    elsif databit="01" then
      i<="0111"; 
    elsif databit="10" then
      i<="1000"; 
    elsif databit="11" then    
      i<="1001";    
    end if; 
 end process;
     
 process(rxrdyn,rxclkbuf)
  begin
    if rxrdyn='1'then
      counter<="000";
      datardbuf<='0';
    elsif rxrdyn='0' and rxclkbuf'event and rxclkbuf='1'then
      if counter>"000" and counter<"010" then
         datardbuf<='1';
         counter<=counter+1;
      elsif counter>="010" then
         counter<=counter;
         datardbuf<='0';
      else
         counter<=counter+1;
      end if;
    end if;
  end process;

  process(rxclkbuf,flag,reset,datainpabuf)
   begin
    if flag='0' or reset='1'then
        j<="0000";
    elsif flag='1' and rxclkbuf'event and rxclkbuf='0'then
        sdataoutbuf<=datainpabuf(conv_integer(j));
        j<=j+1;
    end if;
  end process;

  process(datardbuf,rxclkbuf)
   begin
    if datardbuf='1'then
       counterrx<="0000";
    elsif datardbuf='0' and rxclkbuf'event and rxclkbuf='0'then
      if counterrx=i then
         counterrx<=counterrx;
      else counterrx<=counterrx+1;
      end if;
    end if;
   end process;
  
  process(counterrx,datardbuf,rclk16x,rxclkbuf,i)
   begin
    if datardbuf='1'then
       counterbuf<="00";
    elsif counterrx=i-1 and rxclkbuf='1' then
       if rclk16x'event and rclk16x='1'then
         if counterbuf>"10"then
            counterbuf<=counterbuf;
         else
            counterbuf<=counterbuf+1;
         end if;
       end if;
    end if;
  end process;
  
  process(datardbuf,counterrx,counterbuf,i)
   begin
     if reset='1'then
        flag<='0';
     elsif datardbuf='0' and counterrx<i and counterbuf<"10"then
        flag<='1';
     else
        flag<='0';
     end if;
  end process;  
  
  ds2172rclk<=not (flag and rxclk);
  ds2172dataout<=sdataoutbuf;
  datard<=datardbuf; 
  
end behavioral;