baudrate.vhd

来自「个人原创」· VHDL 代码 · 共 81 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity baudrate is
port(
     reset:in std_logic;
     cs0,cs1:in std_logic;
     nwr:in std_logic;
     clk98m:in std_logic;
     data:in std_logic_vector(7 downto 0);
     baudrate:out std_logic;
     clk16m,clk1m:out std_logic
    );
end;

architecture behavioral of baudrate is

signal databuf:std_logic_vector(15 downto 0);
signal counter:std_logic_vector(15 downto 0);
signal count1:std_logic_vector(1 downto 0);
signal count2:std_logic_vector(2 downto 0);
signal clkbuf:std_logic;
signal clk16mbuf,clk1mbuf:std_logic;

begin
 process(reset,cs0,cs1,nwr)
  begin
    if reset='1'then 
       databuf<="0000000000000100";
    elsif nwr'event and nwr='1'then
       if cs0='0'then
         databuf(7 downto 0)<=data;
       elsif cs1='0'then
         databuf(15 downto 8)<=data;       
       end if;
    end if;
 end process;

 process(clk98m)
  begin
   if clk98m'event and clk98m='1'then
     if counter=databuf then
        counter<=(others=>'0');
        clkbuf<=not clkbuf;
     else
        counter<=counter+1;
     end if;
   end if;
 end process;

 process(clk98m)
  begin
   if clk98m'event and clk98m='1'then
     if count1="10"then
        count1<="00";
        clk16mbuf<=not clk16mbuf;
     else
        count1<=count1+1;
     end if;
   end if;
 end process;

 process(clk16mbuf)
  begin
  if clk16mbuf'event and clk16mbuf='1'then
     if count2="111"then
        count2<="000";
        clk1mbuf<=not clk1mbuf;
     else
        count2<=count2+1;
     end if;
   end if;
 end process;
 
 clk1m<=not clk1mbuf;
 clk16m<=not clk16mbuf;
 baudrate<=clkbuf;
end behavioral;