ds2172tx.vhd

来自「个人原创」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ds2172t is
PORT(
     txclk,reset:in std_logic;
     dataout:out std_logic
    );
end;

architecture behavioral of ds2172t is

signal databuf:std_logic;
signal data:std_logic_vector(7 downto 0);
signal j:integer range 0 to 7;
begin
 

 process(txclk,reset)
   begin
    if reset='1'then
        data<="01110001"; 
    elsif txclk'event and txclk='1'then
       databuf<=data(j);
       if j=7 then
         j<=0;
         data<=data+1;
       else
         j<=j+1;
       end if;
    end if;
 end process;

 dataout<=databuf;
 
end behavioral;