serialtopa.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity serialt is
port(
     reset,txclk,tclk16x,clk98m:in std_logic;
     ncs,nwr,txrdyn:in std_logic;
     addr:in std_logic_vector(2 downto 0);
     datain:in std_logic_vector(1 downto 0);
     ds2172datain:in std_logic;    
     datawr:out std_logic;
     dataout:out std_logic_vector(7 downto 0);
     ds2172tclk:out std_logic     
    );
end;

architecture behavioral of serialt is

signal databit:std_logic_vector(1 downto 0);
signal txactive,txactive1,flag:std_logic;
signal i,j:std_logic_vector(3 downto 0);
signal counter16x:std_logic_vector(2 downto 0);
signal txclkbuf:std_logic;
signal ds2172tclkbuf,ds2172tclkbuf1:std_logic;
signal databuf:std_logic_vector(7 downto 0);

begin
 
 ds2172tclkbuf1<=txclk and txactive1;
 txclkbuf<=txclk and txactive;

 process(clk98m)
  begin
   if clk98m'event and clk98m='0'then
      ds2172tclkbuf<=ds2172tclkbuf1;
   end if;
 end process;

 process(reset,ncs,nwr,addr,datain)
   begin
     if reset='1'then
       databit<="11";
       --databit<="01";         
     elsif nwr'event and nwr='1'then
       if ncs='0' and addr="011"then   
         databit<=datain;
       end if;
     end if;
 end process;

 process(databit,txrdyn)
  begin
    if databit="00" then
      i<="0111"; 
    elsif databit="01" then
      i<="1000"; 
    elsif databit="10" then
      i<="1001"; 
    elsif databit="11" then    
      i<="1010";
    end if;  
 end process; 

 process(txrdyn,reset,flag)
  begin  
    if j>="0001" and j<i then
       txactive1<='1';   
    else
       txactive1<='0';    
    end if;
 end process;

 process(txrdyn,reset,flag)
  begin  
    if j>="0000" and j<i then
       txactive<='1';   
    else
       txactive<='0';    
    end if;
 end process;

 process(txclkbuf,txrdyn,reset,flag)
  begin    
    if txrdyn='1' or reset='1' then
        j<=i;
    elsif txrdyn='0' and j=i then
        j<="0000"; 
    
    elsif txclkbuf'event and txclkbuf='0' and flag='0'then
         
       if j>="0001"then            
        databuf(conv_integer(j-1))<=ds2172datain;
       end if;
        j<=j+1;      
    end if;
    
 end process;
 
 process(i,j,tclk16x,txclk,reset)
  begin
    if reset='1' or j<i-1 then
       counter16x<="000";
       flag<='0';
    elsif tclk16x'event and tclk16x='1' and j=i-1 and txclkbuf='0' then
       counter16x<=counter16x+1; 
       if counter16x>"010" or txactive='1' then         
            counter16x<=counter16x;
            flag<='1';
       end if;
    end if;
 end process; 
 
 datawr<=flag;
 ds2172tclk<=ds2172tclkbuf;
 dataout<=databuf;

end behavioral;