pipdemo.vhd

来自「Flex chip implementation File: UP2FLEX 」· VHDL 代码 · 共 25 行

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-- AND gate (ESD book figure 2.3)		
-- two descriptions provided
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library ieee;
use ieee.std_logic_1164.all;

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entity AND_ent is
port(	x: in std_logic;
	y: in std_logic;
	F: out std_logic
);
end AND_ent;  

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architecture behav2 of AND_ent is
begin

    F <= x and y;

end behav2;