📄 pwm.lst
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ARM COMPILER V2.50a, pwm 08/03/06 18:03:57 PAGE 1
ARM COMPILER V2.50a, COMPILATION OF MODULE pwm
OBJECT MODULE PLACED IN .\Obj\pwm.obj
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe pwm.c THUMB INCDIR(..\Common\inc) DEBUG PRINT(.\LST\PWM.LST) TABS(4) OBJECT(
-.\Obj\pwm.obj)
stmt level source
1 /*****************************************************************************
2 * pwm.c: PWM module file for Philips LPC214x Family Microprocessors
3 *
4 * Copyright(C) 2006, Philips Semiconductor
5 * All rights reserved.
6 *
7 * History
8 * 2005.10.01 ver 1.00 Prelimnary version, first Release
9 *
10 ******************************************************************************/
11 #include "LPC214x.H" /* LPC21xx definitions */
12 #include "type.h"
13 #include "irq.h"
14 #include "timer.h"
15 #include "pwm.h"
16
17 DWORD match_counter;
18
19 /******************************************************************************
20 ** Function name: PWMHandler
21 **
22 ** Descriptions: PWM interrupt handler
23 ** For now, it only deals with PWM match 0
24 **
25 ** parameters: None
26 ** Returned value: None
27 **
28 ******************************************************************************/
29 void PWMHandler (void) __irq
30 {
31 1 DWORD regVal;
32 1
33 1 regVal = PWMIR;
34 1 IENABLE; /* handles nested interrupt */
35 1 if ( regVal & MR0_INT )
36 1 {
37 2 match_counter++;
38 2 }
39 1 PWMIR |= regVal; /* clear interrupt flag on match 0 */
40 1 IDISABLE;
41 1 VICVectAddr = 0; /* Acknowledge Interrupt */
42 1 }
43
44 /******************************************************************************
45 ** Function name: PWM_Init
46 **
47 ** Descriptions: PWM initialization, setup all GPIOs to PWM0~6,
48 ** reset counter, all latches are enabled, interrupt
49 ** on PWMMR0, install PWM interrupt to the VIC table.
50 **
51 ** parameters: Duty cycle
52 ** Returned value: true or fase, if VIC table is full, return false
53 **
54 ******************************************************************************/
55 DWORD PWM_Init( DWORD cycle )
56 {
57 1 match_counter = 0;
58 1 PINSEL0 = 0x000A800A; /* set GPIOs for all PWMs */
ARM COMPILER V2.50a, pwm 08/03/06 18:03:57 PAGE 2
59 1 PINSEL1 = 0x00000400;
60 1
61 1 PWMTCR = TCR_RESET; /* Counter Reset */
62 1
63 1 PWMPR = 0x00; /* count frequency:Fpclk */
64 1 PWMMCR = PWMMR0I | PWMMR0R; /* interrupt on PWMMR0, reset on PWMMR0, reset
65 1 TC if PWM0 matches */
66 1 PWMMR0 = cycle; /* set PWM cycle */
67 1 PWMMR1 = cycle * 5/6;
68 1 PWMMR2 = cycle * 2/3;
69 1 PWMMR3 = cycle * 1/2;
70 1 PWMMR4 = cycle * 1/3;
71 1 PWMMR5 = cycle * 1/6;
72 1
73 1 /* all PWM latch enabled */
74 1 PWMLER = LER0_EN | LER1_EN | LER2_EN | LER3_EN | LER4_EN | LER5_EN | LER6_EN;
75 1
76 1 if ( install_irq( PWM0_INT, (void *)PWMHandler ) == FALSE )
77 1 {
78 2 return (FALSE);
79 2 }
80 1 return (TRUE);
81 1 }
82
83 /******************************************************************************
84 ** Function name: PWM_Set
85 **
86 ** Descriptions: PWM cycle setup
87 **
88 ** parameters: PWM cycle and offset
89 ** Returned value: None
90 **
91 ******************************************************************************/
92 void PWM_Set( DWORD cycle, DWORD offset )
93 {
94 1 PWMMR0 = cycle; /* set PWM cycle */
95 1 PWMMR1 = cycle * 5/6 + offset;
96 1 PWMMR2 = cycle * 2/3 + offset;
97 1 PWMMR3 = cycle * 1/2 + offset;
98 1 PWMMR4 = cycle * 1/3 + offset;
99 1 PWMMR5 = cycle * 1/6 + offset;
100 1
101 1 /* The LER will be cleared when the Match 0 takes place, in order to
102 1 load and execute the new value of match registers, all the PWMLERs need to
103 1 reloaded. all PWM latch enabled */
104 1 PWMLER = LER0_EN | LER1_EN | LER2_EN | LER3_EN | LER4_EN | LER5_EN | LER6_EN;
105 1 return;
106 1 }
107
108 /******************************************************************************
109 ** Function name: PWM_Start
110 **
111 ** Descriptions: Enable PWM by setting the PCR, PTCR registers
112 **
113 ** parameters: None
114 ** Returned value: None
115 **
116 ******************************************************************************/
117 void PWM_Start( void )
118 {
119 1 /* All single edge, all enable */
120 1 PWMPCR = PWMENA1 | PWMENA2 | PWMENA3 | PWMENA4 | PWMENA5 | PWMENA6;
121 1 PWMTCR = TCR_CNT_EN | TCR_PWM_EN; /* counter enable, PWM enable */
122 1 return;
123 1 }
124
ARM COMPILER V2.50a, pwm 08/03/06 18:03:57 PAGE 3
125 /******************************************************************************
126 ** Function name: PWM_Stop
127 **
128 ** Descriptions: Stop all PWM channels
129 **
130 ** parameters: None
131 ** Returned value: None
132 **
133 ******************************************************************************/
134 void PWM_Stop( void )
135 {
136 1 PWMPCR = 0;
137 1 PWMTCR = 0x00; /* Stop all PWMs */
138 1 return;
139 1 }
140
ARM COMPILER V2.50a, pwm 08/03/06 18:03:57 PAGE 4
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN CODE16 (install_irq?T)
EXTERN CODE16 (?C?UDIV?T)
*** PUBLICS:
PUBLIC PWM_Init?T
PUBLIC PWM_Set?T
PUBLIC PWM_Start?T
PUBLIC PWM_Stop?T
PUBLIC PWMHandler?A
PUBLIC match_counter
*** DATA SEGMENT '?DT0?pwm':
00000000 match_counter:
00000000 DS 4
*** CODE SEGMENT '?PR?PWMHandler?A?pwm':
29: void PWMHandler (void) __irq
00000000 E92D400F STMDB R13!,{R0-R3,LR}
30: {
00000004 ; SCOPE-START
33: regVal = PWMIR;
00000004 E5100000 LDR R0,=0xE0014000
00000008 E5903000 LDR R3,[R0,#0x0]
0000000C ---- Variable 'regVal' assigned to Register 'R3' ----
34: IENABLE; /* handles nested interrupt */
0000000C E14FE000 MRS R14,SPSR
00000010 E92D4000 STMFD R13!,{LR}
00000014 E321F01F MSR CPSR_c,#0x1F
00000018 E92D4000 STMFD R13!,{LR}
35: if ( regVal & MR0_INT )
0000001C E1A00003 MOV R0,R3 ; regVal
00000020 E3100001 TST R0,#0x0001 ; regVal
00000024 0A000003 BEQ L_1 ; Targ=0x38
37: match_counter++;
00000028 E5100000 LDR R0,=match_counter ; match_counter
0000002C E5901000 LDR R1,[R0,#0x0] ; match_counter
00000030 E2811001 ADD R1,R1,#0x0001
00000034 E5801000 STR R1,[R0,#0x0] ; match_counter
38: }
00000038 L_1:
39: PWMIR |= regVal; /* clear interrupt flag on match 0 */
00000038 E1A02003 MOV R2,R3 ; regVal
0000003C E5100000 LDR R0,=0xE0014000
00000040 E5901000 LDR R1,[R0,#0x0]
00000044 E1811002 ORR R1,R1,R2 ; regVal
00000048 E5801000 STR R1,[R0,#0x0]
40: IDISABLE;
0000004C E8BD4000 LDMFD R13!,{LR}
00000050 E321F092 MSR CPSR_c,#0x92
00000054 E8BD4000 LDMFD R13!,{LR}
00000058 E16FF00E MSR SPSR_cxsf,R14
41: VICVectAddr = 0; /* Acknowledge Interrupt */
0000005C E3A01000 MOV R1,#0x0
00000060 E5100000 LDR R0,=0xFFFFF030
00000064 E5801000 STR R1,[R0,#0x0]
00000068 ; SCOPE-END
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