📄 irq.lst
字号:
55: VICIntSelect = 0;
00000010 4800 LDR R0,=0xFFFFF00C
00000012 6001 STR R1,[R0,#0x0]
58: for ( i = 0; i < VIC_SIZE; i++ )
00000014 1C08 MOV R0,R1 ; i
00000016 L_8:
60: vect_addr = (DWORD *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + i*4);
00000016 1C03 MOV R3,R0 ; i
00000018 009B LSL R3,R3,#0x2 ; i
0000001A 4800 LDR R4,=0xFFFFF100
0000001C 191C ADD R4,R3,R4
0000001E ---- Variable 'vect_addr' assigned to Register 'R4' ----
61: vect_cntl = (DWORD *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + i*4);
0000001E 4800 LDR R1,=0xFFFFF200
00000020 185B ADD R3,R1
00000022 ---- Variable 'vect_cntl' assigned to Register 'R3' ----
62: *vect_addr = 0;
00000022 2200 MOV R2,#0x0
00000024 1C21 MOV R1,R4 ; vect_addr
00000026 600A STR R2,[R1,#0x0] ; vect_addr
63: *vect_cntl = 0;
00000028 2200 MOV R2,#0x0
0000002A 1C19 MOV R1,R3 ; vect_cntl
0000002C 600A STR R2,[R1,#0x0] ; vect_cntl
64: }
0000002E 3001 ADD R0,#0x1
00000030 1C01 MOV R1,R0 ; i
ARM COMPILER V2.53, irq 24/10/06 20:29:56 PAGE 5
00000032 2910 CMP R1,#0x10 ; i
00000034 D3EF BCC L_8 ; T=0x00000016
67: VICDefVectAddr = (DWORD)DefaultVICHandler;
00000036 4900 LDR R1,=DefaultVICHandler?A ; DefaultVICHandler?A
00000038 4800 LDR R0,=0xFFFFF034
0000003A 6001 STR R1,[R0,#0x0]
68: return;
0000003C ; SCOPE-END
69: }
0000003C BC10 POP {R4}
0000003E 4770 BX R14
00000040 ENDP ; 'init_VIC?T'
*** CODE SEGMENT '?PR?install_irq?T?irq':
84: DWORD install_irq( DWORD IntNumber, void *HandlerAddr )
00000000 B470 PUSH {R4-R6}
00000002 ---- Variable 'HandlerAddr' assigned to Register 'R1' ----
00000002 1C02 MOV R2,R0 ; IntNumber
00000004 ---- Variable 'IntNumber' assigned to Register 'R2' ----
85: {
00000004 ; SCOPE-START
90: VICIntEnClr = 1 << IntNumber; /* Disable Interrupt */
00000004 1C10 MOV R0,R2 ; IntNumber
00000006 2301 MOV R3,#0x1
00000008 4083 LSL R3,R0
0000000A 4800 LDR R0,=0xFFFFF014
0000000C 6003 STR R3,[R0,#0x0]
92: for ( i = 0; i < VIC_SIZE; i++ )
0000000E 2300 MOV R3,#0x0
00000010 ---- Variable 'i' assigned to Register 'R3' ----
00000010 L_14:
96: vect_addr = (DWORD *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + i*4);
00000010 1C1D MOV R5,R3 ; i
00000012 00AD LSL R5,R5,#0x2 ; i
00000014 4800 LDR R6,=0xFFFFF100
00000016 19AE ADD R6,R5,R6
00000018 ---- Variable 'vect_addr' assigned to Register 'R6' ----
97: vect_cntl = (DWORD *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + i*4);
00000018 4800 LDR R0,=0xFFFFF200
0000001A 182D ADD R5,R0
0000001C ---- Variable 'vect_cntl' assigned to Register 'R5' ----
98: if ( *vect_addr == (DWORD)NULL )
0000001C 1C30 MOV R0,R6 ; vect_addr
0000001E 6800 LDR R0,[R0,#0x0] ; vect_addr
00000020 2800 CMP R0,#0x0
00000022 D108 BNE L_11 ; T=0x00000036
100: *vect_addr = (DWORD)HandlerAddr; /* set interrupt vector */
00000024 1C0C MOV R4,R1 ; HandlerAddr
00000026 1C30 MOV R0,R6 ; vect_addr
00000028 6004 STR R4,[R0,#0x0] ; vect_addr
101: *vect_cntl = (DWORD)(IRQ_SLOT_EN | IntNumber);
0000002A 1C14 MOV R4,R2 ; IntNumber
0000002C 2020 MOV R0,#0x20
0000002E 4304 ORR R4,R0
00000030 1C28 MOV R0,R5 ; vect_cntl
00000032 6004 STR R4,[R0,#0x0] ; vect_cntl
102: break;
00000034 E003 B L_12 ; T=0x0000003E
104: }
00000036 L_11:
00000036 3301 ADD R3,#0x1
00000038 1C18 MOV R0,R3 ; i
0000003A 2810 CMP R0,#0x10 ; i
0000003C D3E8 BCC L_14 ; T=0x00000010
0000003E L_12:
105: if ( i == VIC_SIZE )
0000003E 1C18 MOV R0,R3 ; i
ARM COMPILER V2.53, irq 24/10/06 20:29:56 PAGE 6
00000040 2810 CMP R0,#0x10 ; i
00000042 D101 BNE L_17 ; T=0x00000048
107: return( FALSE ); /* fatal error, can't find empty vector slot */
00000044 2000 MOV R0,#0x0
00000046 E005 B L_18 ; T=0x00000054
108: }
00000048 L_17:
109: VICIntEnable = 1 << IntNumber; /* Enable Interrupt */
00000048 1C11 MOV R1,R2 ; IntNumber
0000004A 2001 MOV R0,#0x1
0000004C 1C02 MOV R2,R0
0000004E 408A LSL R2,R1
00000050 4800 LDR R1,=0xFFFFF010
00000052 600A STR R2,[R1,#0x0]
110: return( TRUE );
00000054 ; SCOPE-END
111: }
00000054 L_18:
00000054 BC70 POP {R4-R6}
00000056 4770 BX R14
00000058 ENDP ; 'install_irq?T'
*** CODE SEGMENT '?PR?uninstall_irq?T?irq':
125: DWORD uninstall_irq( DWORD IntNumber )
00000000 B430 PUSH {R4-R5}
00000002 1C02 MOV R2,R0 ; IntNumber
00000004 ---- Variable 'IntNumber' assigned to Register 'R2' ----
126: {
00000004 ; SCOPE-START
131: VICIntEnClr = 1 << IntNumber; /* Disable Interrupt */
00000004 1C10 MOV R0,R2 ; IntNumber
00000006 2101 MOV R1,#0x1
00000008 4081 LSL R1,R0
0000000A 4800 LDR R0,=0xFFFFF014
0000000C 6001 STR R1,[R0,#0x0]
133: for ( i = 0; i < VIC_SIZE; i++ )
0000000E 2100 MOV R1,#0x0
00000010 ---- Variable 'i' assigned to Register 'R1' ----
00000010 L_22:
136: vect_addr = (DWORD *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + i*4);
00000010 1C0C MOV R4,R1 ; i
00000012 00A4 LSL R4,R4,#0x2 ; i
00000014 4800 LDR R5,=0xFFFFF100
00000016 1965 ADD R5,R4,R5
00000018 ---- Variable 'vect_addr' assigned to Register 'R5' ----
137: vect_cntl = (DWORD *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + i*4);
00000018 4800 LDR R0,=0xFFFFF200
0000001A 1824 ADD R4,R0
0000001C ---- Variable 'vect_cntl' assigned to Register 'R4' ----
138: if ( (*vect_cntl & ~IRQ_SLOT_EN ) == IntNumber )
0000001C 1C20 MOV R0,R4 ; vect_cntl
0000001E 6803 LDR R3,[R0,#0x0] ; vect_cntl
00000020 2020 MOV R0,#0x20
00000022 4383 BIC R3,R0
00000024 1C10 MOV R0,R2 ; IntNumber
00000026 4283 CMP R3,R0 ; IntNumber
00000028 D109 BNE L_19 ; T=0x0000003E
140: *vect_addr = (DWORD)NULL; /* clear the VIC entry in the VIC table */
0000002A 2300 MOV R3,#0x0
0000002C 1C28 MOV R0,R5 ; vect_addr
0000002E 6003 STR R3,[R0,#0x0] ; vect_addr
141: *vect_cntl &= ~IRQ_SLOT_EN; /* disable SLOT_EN bit */
00000030 1C20 MOV R0,R4 ; vect_cntl
00000032 6803 LDR R3,[R0,#0x0] ; vect_cntl
00000034 2020 MOV R0,#0x20
00000036 4383 BIC R3,R0
00000038 1C20 MOV R0,R4 ; vect_cntl
ARM COMPILER V2.53, irq 24/10/06 20:29:56 PAGE 7
0000003A 6003 STR R3,[R0,#0x0] ; vect_cntl
142: break;
0000003C E003 B L_20 ; T=0x00000046
144: }
0000003E L_19:
0000003E 3101 ADD R1,#0x1
00000040 1C08 MOV R0,R1 ; i
00000042 2810 CMP R0,#0x10 ; i
00000044 D3E4 BCC L_22 ; T=0x00000010
00000046 L_20:
145: if ( i == VIC_SIZE )
00000046 1C08 MOV R0,R1 ; i
00000048 2810 CMP R0,#0x10 ; i
0000004A D101 BNE L_25 ; T=0x00000050
147: return( FALSE ); /* fatal error, can't find interrupt number
0000004C 2000 MOV R0,#0x0
0000004E E005 B L_26 ; T=0x0000005C
149: }
00000050 L_25:
150: VICIntEnable = 1 << IntNumber; /* Enable Interrupt */
00000050 1C11 MOV R1,R2 ; IntNumber
00000052 2001 MOV R0,#0x1
00000054 1C02 MOV R2,R0
00000056 408A LSL R2,R1
00000058 4800 LDR R1,=0xFFFFF010
0000005A 600A STR R2,[R1,#0x0]
151: return( TRUE );
0000005C ; SCOPE-END
152: }
0000005C L_26:
0000005C BC30 POP {R4-R5}
0000005E 4770 BX R14
00000060 ENDP ; 'uninstall_irq?T'
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -