📄 temp.lst
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1 .file "temp.c"
2 .arch atmega128
3 __SREG__ = 0x3f
4 __SP_H__ = 0x3e
5 __SP_L__ = 0x3d
6 __tmp_reg__ = 0
7 __zero_reg__ = 1
8 .global __do_copy_data
9 .global __do_clear_bss
12 .text
13 .Ltext0:
91 .global spi_initial
93 spi_initial:
1:temp.c **** #include <avr/io.h>
2:temp.c **** #include <stdlib.h>
3:temp.c **** #include <avr/signal.h>
4:temp.c **** #include <avr/interrupt.h>
5:temp.c **** #include <avr/delay.h>
6:temp.c **** #include <pgmspace.h>
7:temp.c **** #include <avr/io.h>
8:temp.c **** #include <stdlib.h>
9:temp.c **** #include <avr/signal.h>
10:temp.c **** #include <avr/interrupt.h>
11:temp.c **** #include <avr/delay.h>
12:temp.c **** #include <pgmspace.h>
13:temp.c **** #define N 10
14:temp.c **** #define FREQ 14.7456
15:temp.c **** #define uchar uint8_t
16:temp.c ****
17:temp.c **** //硬件引脚定义
18:temp.c **** //READ
19:temp.c **** #define READ_STATE_REGISTER 0xd7
20:temp.c **** #define MAIN_MEMORY_PAGE_READ 0xd2
21:temp.c **** #define BUFFER_1_READ 0xd4
22:temp.c **** #define BUFFER_2_READ 0xd6
23:temp.c **** //ERASE
24:temp.c **** #define SECTOR_ERASE 0x7c
25:temp.c **** #define PAGE_ERASE 0x81
26:temp.c **** #define BLOCK_ERASE 0x50
27:temp.c **** //WRITE
28:temp.c **** #define BUFFER_1_WRITE 0x84
29:temp.c **** #define BUFFER_2_WRITE 0x87
30:temp.c **** #define B1_TO_MM_PAGE_PROG_WITH_ERASE 0x83
31:temp.c **** #define B2_TO_MM_PAGE_PROG_WITH_ERASE 0x86
32:temp.c **** #define MM_PAGE_PROG_THROUGH_B1 0x82
33:temp.c **** #define MM_PAGE_PROG_THROUGH_B2 0x85
34:temp.c **** //OTHER
35:temp.c **** #define MM_PAGE_TO_B1_XFER 0x53
36:temp.c **** #define MM_PAGE_TO_B2_XFER 0x55
37:temp.c ****
38:temp.c **** #define FLASH_PAGE_COUNT 8192
39:temp.c **** #define FLASH_PAGE_SIZE 1056
40:temp.c ****
41:temp.c **** #define MOSI_L cbi(PORTB,2)
42:temp.c **** #define MOSI_H sbi(PORTB,2)
43:temp.c ****
44:temp.c **** #define SCK_L cbi(PORTB,1)
45:temp.c **** #define SCK_H sbi(PORTB,1)
46:temp.c ****
47:temp.c **** #define FLASH_RES_L cbi(PORTE,4)
48:temp.c **** #define FLASH_RES_H sbi(PORTE,4)
49:temp.c **** #define WP_L cbi(PORTE,3)
50:temp.c **** #define WP_H sbi(PORTE,3)
51:temp.c ****
52:temp.c **** #define FLASH_CS_L cbi(PORTE,2)
53:temp.c **** #define FLASH_CS_H sbi(PORTE,2)
54:temp.c **** #define SS_H sbi(PORTB,0)
55:temp.c **** #define SS_L cbi(PORTB,0)
56:temp.c ****
57:temp.c **** #define DF_SELECT_1 FLASH_CS_L
58:temp.c **** #define DF_DESELECT_1 FLASH_CS_H
59:temp.c ****
60:temp.c **** void spi_initial(void)
61:temp.c **** {
95 .LM1:
96 /* prologue: frame size=1 */
97 0000 CF93 push r28
98 0002 DF93 push r29
99 0004 CDB7 in r28,__SP_L__
100 0006 DEB7 in r29,__SP_H__
101 0008 2197 sbiw r28,1
102 000a 0FB6 in __tmp_reg__,__SREG__
103 000c F894 cli
104 000e DEBF out __SP_H__,r29
105 0010 0FBE out __SREG__,__tmp_reg__
106 0012 CDBF out __SP_L__,r28
107 /* prologue end (size=10) */
62:temp.c **** uint8_t temp;
63:temp.c **** DDRB |= 0x07; //MISO=input and MOSI,SCK,SS = output
109 .LM2:
110 .LBB2:
111 0014 8091 3700 lds r24,55
112 0018 8760 ori r24,lo8(7)
113 001a 8093 3700 sts 55,r24
64:temp.c **** PORTB |= 0x0f; //MISO上拉电阻有效
115 .LM3:
116 001e 8091 3800 lds r24,56
117 0022 8F60 ori r24,lo8(15)
118 0024 8093 3800 sts 56,r24
65:temp.c **** SPCR = 0x5c; //SPI允许，主机模式，MSB
120 .LM4:
121 0028 8CE5 ldi r24,lo8(92)
122 002a 8093 2D00 sts 45,r24
66:temp.c **** SPSR = 0x00;
124 .LM5:
125 002e 1092 2E00 sts 46,__zero_reg__
67:temp.c **** temp = SPSR;
127 .LM6:
128 0032 8091 2E00 lds r24,46
129 0036 8983 std Y+1,r24
68:temp.c **** temp = SPDR; //清空SPI，和中断标志，使SPI空闲
131 .LM7:
132 0038 8091 2F00 lds r24,47
133 003c 8983 std Y+1,r24
69:temp.c ****
70:temp.c **** }
135 .LM8:
136 .LBE2:
137 /* epilogue: frame size=1 */
138 003e 2196 adiw r28,1
139 0040 0FB6 in __tmp_reg__,__SREG__
140 0042 F894 cli
141 0044 DEBF out __SP_H__,r29
142 0046 0FBE out __SREG__,__tmp_reg__
143 0048 CDBF out __SP_L__,r28
144 004a DF91 pop r29
145 004c CF91 pop r28
146 004e 0895 ret
147 /* epilogue end (size=9) */
148 /* function spi_initial size 40 (21) */
153 .Lscope0:
157 .global write_SPI
159 write_SPI:
71:temp.c **** uint8_t write_SPI(uint8_t c)
72:temp.c **** {
161 .LM9:
162 /* prologue: frame size=2 */
163 0050 CF93 push r28
164 0052 DF93 push r29
165 0054 CDB7 in r28,__SP_L__
166 0056 DEB7 in r29,__SP_H__
167 0058 2297 sbiw r28,2
168 005a 0FB6 in __tmp_reg__,__SREG__
169 005c F894 cli
170 005e DEBF out __SP_H__,r29
171 0060 0FBE out __SREG__,__tmp_reg__
172 0062 CDBF out __SP_L__,r28
173 /* prologue end (size=10) */
174 0064 8983 std Y+1,r24
73:temp.c **** uint8_t data;
74:temp.c **** SPDR=c;
176 .LM10:
177 .LBB3:
178 0066 8981 ldd r24,Y+1
179 0068 8093 2F00 sts 47,r24
75:temp.c **** while((SPSR&0x80)==0);
181 .LM11:
182 .L11:
183 006c 8091 2E00 lds r24,46
184 0070 8823 tst r24
185 0072 E4F7 brge .L11
76:temp.c **** data=SPDR;
187 .LM12:
188 0074 8091 2F00 lds r24,47
189 0078 8A83 std Y+2,r24
77:temp.c **** return data;
191 .LM13:
192 007a 8A81 ldd r24,Y+2
193 007c 9927 clr r25
78:temp.c **** }
195 .LM14:
196 .LBE3:
197 /* epilogue: frame size=2 */
198 007e 2296 adiw r28,2
199 0080 0FB6 in __tmp_reg__,__SREG__
200 0082 F894 cli
201 0084 DEBF out __SP_H__,r29
202 0086 0FBE out __SREG__,__tmp_reg__
203 0088 CDBF out __SP_L__,r28
204 008a DF91 pop r29
205 008c CF91 pop r28
206 008e 0895 ret
207 /* epilogue end (size=9) */
208 /* function write_SPI size 32 (13) */
213 .Lscope1:
217 .global Host_write_SPI
219 Host_write_SPI:
79:temp.c **** void Host_write_SPI(uint8_t c)
80:temp.c **** {
221 .LM15:
222 /* prologue: frame size=1 */
223 0090 CF93 push r28
224 0092 DF93 push r29
225 0094 CDB7 in r28,__SP_L__
226 0096 DEB7 in r29,__SP_H__
227 0098 2197 sbiw r28,1
228 009a 0FB6 in __tmp_reg__,__SREG__
229 009c F894 cli
230 009e DEBF out __SP_H__,r29
231 00a0 0FBE out __SREG__,__tmp_reg__
232 00a2 CDBF out __SP_L__,r28
233 /* prologue end (size=10) */
234 00a4 8983 std Y+1,r24
81:temp.c **** SPDR=c;
236 .LM16:
237 00a6 8981 ldd r24,Y+1
238 00a8 8093 2F00 sts 47,r24
82:temp.c **** while((SPSR&0x80)==0);
240 .LM17:
241 .L15:
242 00ac 8091 2E00 lds r24,46
243 00b0 8823 tst r24
244 00b2 E4F7 brge .L15
83:temp.c **** }
246 .LM18:
247 /* epilogue: frame size=1 */
248 00b4 2196 adiw r28,1
249 00b6 0FB6 in __tmp_reg__,__SREG__
250 00b8 F894 cli
251 00ba DEBF out __SP_H__,r29
252 00bc 0FBE out __SREG__,__tmp_reg__
253 00be CDBF out __SP_L__,r28
254 00c0 DF91 pop r29
255 00c2 CF91 pop r28
256 00c4 0895 ret
257 /* epilogue end (size=9) */
258 /* function Host_write_SPI size 27 (8) */
260 .Lscope2:
263 .global df_init
265 df_init:
84:temp.c **** void df_init(void)
85:temp.c **** {
267 .LM19:
268 /* prologue: frame size=0 */
269 00c6 CF93 push r28
270 00c8 DF93 push r29
271 00ca CDB7 in r28,__SP_L__
272 00cc DEB7 in r29,__SP_H__
273 /* prologue end (size=4) */
86:temp.c **** cbi(DDRE,1);
275 .LM20:
276 00ce 8091 2200 lds r24,34
277 00d2 8D7F andi r24,lo8(-3)
278 00d4 8093 2200 sts 34,r24
87:temp.c **** sbi(PORTE,1);
280 .LM21:
281 00d8 8091 2300 lds r24,35
282 00dc 8260 ori r24,lo8(2)
283 00de 8093 2300 sts 35,r24
88:temp.c **** cbi(DDRE,0);
285 .LM22:
286 00e2 8091 2200 lds r24,34
287 00e6 8E7F andi r24,lo8(-2)
288 00e8 8093 2200 sts 34,r24
89:temp.c **** sbi(PORTE,0);
290 .LM23:
291 00ec 8091 2300 lds r24,35
292 00f0 8160 ori r24,lo8(1)
293 00f2 8093 2300 sts 35,r24
90:temp.c ****
91:temp.c **** spi_initial();
295 .LM24:
296 00f6 0E94 0000 call spi_initial
92:temp.c **** cbi(DDRE,5);//RDY
298 .LM25:
299 00fa 8091 2200 lds r24,34
300 00fe 8F7D andi r24,lo8(-33)
301 0100 8093 2200 sts 34,r24
93:temp.c **** sbi(PORTE,5);
303 .LM26:
304 0104 8091 2300 lds r24,35
305 0108 8062 ori r24,lo8(32)
306 010a 8093 2300 sts 35,r24
94:temp.c **** sbi(DDRE,2);//CS
308 .LM27:
309 010e 8091 2200 lds r24,34
310 0112 8460 ori r24,lo8(4)
311 0114 8093 2200 sts 34,r24
95:temp.c **** FLASH_CS_H;
313 .LM28:
314 0118 8091 2300 lds r24,35
315 011c 8460 ori r24,lo8(4)
316 011e 8093 2300 sts 35,r24
96:temp.c **** sbi(DDRE,4);//RES
318 .LM29:
319 0122 8091 2200 lds r24,34
320 0126 8061 ori r24,lo8(16)
321 0128 8093 2200 sts 34,r24
97:temp.c **** FLASH_RES_H;
323 .LM30:
324 012c 8091 2300 lds r24,35
325 0130 8061 ori r24,lo8(16)
326 0132 8093 2300 sts 35,r24
98:temp.c **** sbi(DDRE,3);//WP
328 .LM31:
329 0136 8091 2200 lds r24,34
330 013a 8860 ori r24,lo8(8)
331 013c 8093 2200 sts 34,r24
99:temp.c **** WP_H;
333 .LM32:
334 0140 8091 2300 lds r24,35
335 0144 8860 ori r24,lo8(8)
336 0146 8093 2300 sts 35,r24
100:temp.c **** }
338 .LM33:
339 /* epilogue: frame size=0 */
340 014a DF91 pop r29
341 014c CF91 pop r28
342 014e 0895 ret
343 /* epilogue end (size=3) */
344 /* function df_init size 69 (62) */
346 .Lscope3:
349 .global DF_read_reg
351 DF_read_reg:
101:temp.c **** uint8_t DF_read_reg(void)
102:temp.c **** {
353 .LM34:
354 /* prologue: frame size=1 */
355 0150 CF93 push r28
356 0152 DF93 push r29
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