period_led.map.qmsg

来自「LED周期闪烁」· QMSG 代码 · 共 10 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 11 15:58:16 2008 " "Info: Processing started: Tue Nov 11 15:58:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off period_led -c period_led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off period_led -c period_led" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "period_led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file period_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 period_led " "Info: Found entity 1: period_led" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "period_led " "Info: Elaborating entity \"period_led\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 period_led.v(9) " "Warning (10230): Verilog HDL assignment warning at period_led.v(9): truncated value with size 32 to match size of target (24)" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "LED\[0\]~reg0 LED\[7\]~reg0 " "Info: Duplicate register \"LED\[0\]~reg0\" merged to single register \"LED\[7\]~reg0\"" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LED\[3\]~reg0 LED\[7\]~reg0 " "Info: Duplicate register \"LED\[3\]~reg0\" merged to single register \"LED\[7\]~reg0\"" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LED\[6\]~reg0 LED\[7\]~reg0 " "Info: Duplicate register \"LED\[6\]~reg0\" merged to single register \"LED\[7\]~reg0\"" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LED\[4\]~reg0 LED\[7\]~reg0 " "Info: Duplicate register \"LED\[4\]~reg0\" merged to single register \"LED\[7\]~reg0\"" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LED\[2\]~reg0 LED\[7\]~reg0 " "Info: Duplicate register \"LED\[2\]~reg0\" merged to single register \"LED\[7\]~reg0\"" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LED\[5\]~reg0 LED\[7\]~reg0 " "Info: Duplicate register \"LED\[5\]~reg0\" merged to single register \"LED\[7\]~reg0\"" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LED\[1\]~reg0 LED\[7\]~reg0 " "Info: Duplicate register \"LED\[1\]~reg0\" merged to single register \"LED\[7\]~reg0\"" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "65 " "Info: Implemented 65 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "56 " "Info: Implemented 56 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "123 " "Info: Allocated 123 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 11 15:58:17 2008 " "Info: Processing ended: Tue Nov 11 15:58:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}