period_led.tan.qmsg

LED周期闪烁

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register counter\[20\] register counter\[23\] 198.85 MHz 5.029 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 198.85 MHz between source register \"counter\[20\]\" and destination register \"counter\[23\]\" (period= 5.029 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.768 ns + Longest register register " "Info: + Longest register to register delay is 4.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[20\] 1 REG LC_X10_Y11_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y11_N1; Fanout = 4; REG Node = 'counter\[20\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[20] } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.273 ns) + CELL(0.442 ns) 1.715 ns Equal0~240 2 COMB LC_X11_Y10_N8 1 " "Info: 2: + IC(1.273 ns) + CELL(0.442 ns) = 1.715 ns; Loc. = LC_X11_Y10_N8; Fanout = 1; COMB Node = 'Equal0~240'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.715 ns" { counter[20] Equal0~240 } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.292 ns) 3.228 ns Equal0~244 3 COMB LC_X10_Y11_N3 9 " "Info: 3: + IC(1.221 ns) + CELL(0.292 ns) = 3.228 ns; Loc. = LC_X10_Y11_N3; Fanout = 9; COMB Node = 'Equal0~244'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.513 ns" { Equal0~240 Equal0~244 } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.309 ns) 4.768 ns counter\[23\] 4 REG LC_X11_Y10_N7 2 " "Info: 4: + IC(1.231 ns) + CELL(0.309 ns) = 4.768 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'counter\[23\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.540 ns" { Equal0~244 counter[23] } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.043 ns ( 21.88 % ) " "Info: Total cell delay = 1.043 ns ( 21.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.725 ns ( 78.13 % ) " "Info: Total interconnect delay = 3.725 ns ( 78.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.768 ns" { counter[20] Equal0~240 Equal0~244 counter[23] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "4.768 ns" { counter[20] Equal0~240 Equal0~244 counter[23] } { 0.000ns 1.273ns 1.221ns 1.231ns } { 0.000ns 0.442ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.925 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns counter\[23\] 2 REG LC_X11_Y10_N7 2 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'counter\[23\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { CLK counter[23] } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK counter[23] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 counter[23] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns counter\[20\] 2 REG LC_X10_Y11_N1 4 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y11_N1; Fanout = 4; REG Node = 'counter\[20\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { CLK counter[20] } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK counter[20] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 counter[20] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK counter[23] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 counter[23] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK counter[20] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 counter[20] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.768 ns" { counter[20] Equal0~240 Equal0~244 counter[23] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "4.768 ns" { counter[20] Equal0~240 Equal0~244 counter[23] } { 0.000ns 1.273ns 1.221ns 1.231ns } { 0.000ns 0.442ns 0.292ns 0.309ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK counter[23] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 counter[23] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK counter[20] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 counter[20] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LED\[5\] LED\[7\]~reg0 8.967 ns register " "Info: tco from clock \"CLK\" to destination pin \"LED\[5\]\" through register \"LED\[7\]~reg0\" is 8.967 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.925 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns LED\[7\]~reg0 2 REG LC_X10_Y11_N0 9 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y11_N0; Fanout = 9; REG Node = 'LED\[7\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { CLK LED[7]~reg0 } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK LED[7]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 LED[7]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.818 ns + Longest register pin " "Info: + Longest register to pin delay is 5.818 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED\[7\]~reg0 1 REG LC_X10_Y11_N0 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y11_N0; Fanout = 9; REG Node = 'LED\[7\]~reg0'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { LED[7]~reg0 } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.694 ns) + CELL(2.124 ns) 5.818 ns LED\[5\] 2 PIN PIN_8 0 " "Info: 2: + IC(3.694 ns) + CELL(2.124 ns) = 5.818 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'LED\[5\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.818 ns" { LED[7]~reg0 LED[5] } "NODE_NAME" } } { "period_led.v" "" { Text "D:/Program Files/quartus/Design/period_led/period_led.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 36.51 % ) " "Info: Total cell delay = 2.124 ns ( 36.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.694 ns ( 63.49 % ) " "Info: Total interconnect delay = 3.694 ns ( 63.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.818 ns" { LED[7]~reg0 LED[5] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.818 ns" { LED[7]~reg0 LED[5] } { 0.000ns 3.694ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { CLK LED[7]~reg0 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { CLK CLK~out0 LED[7]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.818 ns" { LED[7]~reg0 LED[5] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.818 ns" { LED[7]~reg0 LED[5] } { 0.000ns 3.694ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 11 15:58:31 2008 " "Info: Processing ended: Tue Nov 11 15:58:31 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}