period_led.tan.rpt

LED周期闪烁

; N/A                                     ; 262.19 MHz ( period = 3.814 ns )                    ; counter[2]  ; counter[12] ; CLK        ; CLK      ; None                        ; None                      ; 3.553 ns                ;
; N/A                                     ; 263.02 MHz ( period = 3.802 ns )                    ; counter[2]  ; counter[22] ; CLK        ; CLK      ; None                        ; None                      ; 3.541 ns                ;
; N/A                                     ; 263.50 MHz ( period = 3.795 ns )                    ; counter[7]  ; counter[13] ; CLK        ; CLK      ; None                        ; None                      ; 3.534 ns                ;
; N/A                                     ; 263.99 MHz ( period = 3.788 ns )                    ; counter[3]  ; counter[12] ; CLK        ; CLK      ; None                        ; None                      ; 3.527 ns                ;
; N/A                                     ; 263.99 MHz ( period = 3.788 ns )                    ; counter[6]  ; counter[13] ; CLK        ; CLK      ; None                        ; None                      ; 3.527 ns                ;
; N/A                                     ; 263.99 MHz ( period = 3.788 ns )                    ; counter[12] ; LED[7]~reg0 ; CLK        ; CLK      ; None                        ; None                      ; 3.527 ns                ;
; N/A                                     ; 264.55 MHz ( period = 3.780 ns )                    ; counter[2]  ; counter[8]  ; CLK        ; CLK      ; None                        ; None                      ; 3.519 ns                ;
; N/A                                     ; 264.83 MHz ( period = 3.776 ns )                    ; counter[3]  ; counter[22] ; CLK        ; CLK      ; None                        ; None                      ; 3.515 ns                ;
; N/A                                     ; 265.04 MHz ( period = 3.773 ns )                    ; counter[5]  ; counter[13] ; CLK        ; CLK      ; None                        ; None                      ; 3.512 ns                ;
; N/A                                     ; 265.11 MHz ( period = 3.772 ns )                    ; counter[7]  ; counter[11] ; CLK        ; CLK      ; None                        ; None                      ; 3.511 ns                ;
; N/A                                     ; 265.89 MHz ( period = 3.761 ns )                    ; counter[0]  ; counter[11] ; CLK        ; CLK      ; None                        ; None                      ; 3.500 ns                ;
; N/A                                     ; 266.24 MHz ( period = 3.756 ns )                    ; counter[23] ; counter[12] ; CLK        ; CLK      ; None                        ; None                      ; 3.495 ns                ;
; N/A                                     ; 266.24 MHz ( period = 3.756 ns )                    ; counter[23] ; counter[9]  ; CLK        ; CLK      ; None                        ; None                      ; 3.495 ns                ;
; N/A                                     ; 266.38 MHz ( period = 3.754 ns )                    ; counter[3]  ; counter[8]  ; CLK        ; CLK      ; None                        ; None                      ; 3.493 ns                ;
; N/A                                     ; 266.81 MHz ( period = 3.748 ns )                    ; counter[12] ; counter[14] ; CLK        ; CLK      ; None                        ; None                      ; 3.487 ns                ;
; N/A                                     ; 266.81 MHz ( period = 3.748 ns )                    ; counter[23] ; counter[7]  ; CLK        ; CLK      ; None                        ; None                      ; 3.487 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; counter[21] ; LED[7]~reg0 ; CLK        ; CLK      ; None                        ; None                      ; 3.483 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;             ;             ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 8.967 ns   ; LED[7]~reg0 ; LED[5] ; CLK        ;
; N/A   ; None         ; 8.967 ns   ; LED[7]~reg0 ; LED[4] ; CLK        ;
; N/A   ; None         ; 8.967 ns   ; LED[7]~reg0 ; LED[3] ; CLK        ;
; N/A   ; None         ; 8.956 ns   ; LED[7]~reg0 ; LED[7] ; CLK        ;
; N/A   ; None         ; 8.956 ns   ; LED[7]~reg0 ; LED[6] ; CLK        ;
; N/A   ; None         ; 8.579 ns   ; LED[7]~reg0 ; LED[0] ; CLK        ;
; N/A   ; None         ; 8.250 ns   ; LED[7]~reg0 ; LED[2] ; CLK        ;
; N/A   ; None         ; 8.250 ns   ; LED[7]~reg0 ; LED[1] ; CLK        ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Nov 11 15:58:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off period_led -c period_led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 198.85 MHz between source register "counter[20]" and destination register "counter[23]" (period= 5.029 ns)
    Info: + Longest register to register delay is 4.768 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y11_N1; Fanout = 4; REG Node = 'counter[20]'
        Info: 2: + IC(1.273 ns) + CELL(0.442 ns) = 1.715 ns; Loc. = LC_X11_Y10_N8; Fanout = 1; COMB Node = 'Equal0~240'
        Info: 3: + IC(1.221 ns) + CELL(0.292 ns) = 3.228 ns; Loc. = LC_X10_Y11_N3; Fanout = 9; COMB Node = 'Equal0~244'
        Info: 4: + IC(1.231 ns) + CELL(0.309 ns) = 4.768 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'counter[23]'
        Info: Total cell delay = 1.043 ns ( 21.88 % )
        Info: Total interconnect delay = 3.725 ns ( 78.13 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'counter[23]'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y11_N1; Fanout = 4; REG Node = 'counter[20]'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK" to destination pin "LED[5]" through register "LED[7]~reg0" is 8.967 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y11_N0; Fanout = 9; REG Node = 'LED[7]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.818 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y11_N0; Fanout = 9; REG Node = 'LED[7]~reg0'
        Info: 2: + IC(3.694 ns) + CELL(2.124 ns) = 5.818 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'LED[5]'
        Info: Total cell delay = 2.124 ns ( 36.51 % )
        Info: Total interconnect delay = 3.694 ns ( 63.49 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Tue Nov 11 15:58:31 2008
    Info: Elapsed time: 00:00:00