period_led.fit.smsg

LED周期闪烁

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Nov 11 15:58:20 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off period_led -c period_led
Info: Selected device EP1C6Q240C8 for design "period_led"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 65 of 65 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~LVDS14p/INIT_DONE~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "CLK" to use Global clock in PIN 28
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.299 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y11; Fanout = 4; REG Node = 'counter[12]'
    Info: 2: + IC(0.874 ns) + CELL(0.590 ns) = 1.464 ns; Loc. = LAB_X10_Y12; Fanout = 1; COMB Node = 'Equal0~242'
    Info: 3: + IC(1.043 ns) + CELL(0.292 ns) = 2.799 ns; Loc. = LAB_X10_Y11; Fanout = 9; COMB Node = 'Equal0~244'
    Info: 4: + IC(0.893 ns) + CELL(0.607 ns) = 4.299 ns; Loc. = LAB_X11_Y10; Fanout = 2; REG Node = 'counter[23]'
    Info: Total cell delay = 1.489 ns ( 34.64 % )
    Info: Total interconnect delay = 2.810 ns ( 65.36 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y11 to location X11_Y21
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 166 megabytes of memory during processing
    Info: Processing ended: Tue Nov 11 15:58:24 2008
    Info: Elapsed time: 00:00:04