reset.s

LPC2102的keil vendor code

;/*****************************************************************************
;*   reset.s reset vector table for NXP LPC23xx/24xx Family Microprocessors
;*
;*   Copyright(C) 2006, NXP Semiconductor
;*   All rights reserved.
;*
;*   History
;*   2007.05.13  ver 1.00    Prelimnary version, first Release
;*
;****************************************************************************/
     PRESERVE8 ; preserve 8-byte stack for procedure call standard 

; define Modes and Interrupt flags to configure Progrm Status Register

USR_Mode        EQU     0x10
FIQ_Mode        EQU     0x11
IRQ_Mode        EQU     0x12
SVC_Mode        EQU     0x13
ABT_Mode        EQU     0x17
UND_Mode        EQU     0x1B
SYS_Mode        EQU     0x1F

I_Bit           EQU     0x80        ; disables IRQ  when true(1)
F_Bit           EQU     0x40        ; disables FIQ  when true(1)
No_INT          EQU     0xC0        ; disables FIQ  and IRQ

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
        AREA    STACK, READWRITE, ALIGN=4

; define Heap & Stack sizes
	   EXPORT  Heap_Bottom
	   EXPORT  USR_Stack_Bottom
	   EXPORT  UND_Stack_Bottom
	   EXPORT  SVC_Stack_Bottom
	   EXPORT  ABT_Stack_Bottom
	   EXPORT  FIQ_Stack_Bottom
	   EXPORT  IRQ_Stack_Bottom

UND_Stack_Size  EQU     0x00000000	 
SVC_Stack_Size  EQU     0x00000100
ABT_Stack_Size  EQU     0x00000000
FIQ_Stack_Size  EQU     0x00000000
IRQ_Stack_Size  EQU     0x00000100
USR_Stack_Size  EQU     0x00000400
SYS_Stack_Size  EQU     0x00000000
Heap_Size       EQU     0x00000100

USR_Stack_Top 	  EQU     USR_Stack_Bottom + USR_Stack_Size
UND_Stack_Top 	  EQU     UND_Stack_Bottom + UND_Stack_Size
SVC_Stack_Top 	  EQU     SVC_Stack_Bottom + SVC_Stack_Size
ABT_Stack_Top 	  EQU     ABT_Stack_Bottom + ABT_Stack_Size
FIQ_Stack_Top 	  EQU     FIQ_Stack_Bottom + FIQ_Stack_Size
IRQ_Stack_Top 	  EQU     IRQ_Stack_Bottom + IRQ_Stack_Size
Heap_Top          EQU     Heap_Bottom + Heap_Size

  
UND_Stack_Bottom   SPACE  UND_Stack_Size
ABT_Stack_Bottom   SPACE  ABT_Stack_Size
FIQ_Stack_Bottom   SPACE  FIQ_Stack_Size

Heap_Bottom        SPACE  Heap_Size
USR_Stack_Bottom   SPACE  USR_Stack_Size
SVC_Stack_Bottom   SPACE  SVC_Stack_Size
IRQ_Stack_Bottom   SPACE  IRQ_Stack_Size

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Overlay List
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	AREA	overlay_list, DATA, READONLY

	; Linker-defined symbols to use
	
	IMPORT ||Load$$RW_IRAM1$$Base||
	IMPORT ||Load$$RW_IRAM2$$Base||

	IMPORT ||Image$$RW_IRAM1$$Base||
	IMPORT ||Image$$RW_IRAM1$$ZI$$Base||
	IMPORT ||Image$$RW_IRAM2$$ZI$$Base||

	IMPORT ||Image$$RW_IRAM1$$ZI$$Length||
	IMPORT ||Image$$RW_IRAM2$$ZI$$Length||

	; Symbols to export
	
	EXPORT data_base
	EXPORT overlay_regions

; Common base execution addresses of the two OVERLAY regions

data_base DCD ||Image$$RW_IRAM1$$Base||

; Array of details for each region -
; see overlay_manager.c for structure layout

overlay_regions
; overlay 1
	DCD ||Load$$RW_IRAM1$$Base||
	DCD ||Image$$RW_IRAM1$$ZI$$Base||
	DCD ||Image$$RW_IRAM1$$ZI$$Length||
	
; overlay 2	
	DCD ||Load$$RW_IRAM2$$Base||
	DCD ||Image$$RW_IRAM2$$ZI$$Base||
	DCD ||Image$$RW_IRAM2$$ZI$$Length||
  
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Reset Handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
        AREA    RESET, CODE, READONLY
        ARM		; ARM mode

;  This section must be first in scatterloading file at 0x00000000
;  Unused modes use infinite loop as Handler.
		 EXPORT Reset_Handler

VectorTable
        LDR     PC, Reset_Addr         
        LDR     PC, Undef_Addr
        LDR     PC, SWI_Addr
        LDR     PC, PAbt_Addr
        LDR     PC, DAbt_Addr
        NOP                            ; check sum for NXP parts 
        LDR     PC, [PC, #-0x0FF0]     ; Vector from VicVectAddr
        LDR     PC, FIQ_Addr

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
;                DCD     0                      ; Reserved Address 
;IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler

Undef_Handler   B       Undef_Handler
SWI_Handler     B       SWI_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
;IRQ_Handler     B       IRQ_Handler
FIQ_Handler     B       FIQ_Handler


Reset_Handler   

;  Set Stack Pointer  UND defined Mode
        MSR     CPSR_c, #UND_Mode|No_INT
        LDR     SP, UND_Stack_Top_Addr

;  Set Stack Pointer  ABT Abort Mode 
        MSR     CPSR_c, #ABT_Mode|No_INT
        LDR     SP, ABT_Stack_Top_Addr

;  Set Stack Pointer FIQ Mode 
        MSR     CPSR_c, #FIQ_Mode|No_INT
        LDR     SP, FIQ_Stack_Top_Addr

;  Set Stack Pointer IRQ Mode 
        MSR     CPSR_c, #IRQ_Mode|No_INT
        LDR     SP, IRQ_Stack_Top_Addr

;  Set Stack Pointer Supervisor Mode
        MSR     CPSR_c, #SVC_Mode|No_INT
        LDR     SP, SVC_Stack_Top_Addr

;  Enter User(SYS) Mode and set its Stack Pointer
        MSR     CPSR_c, #SYS_Mode
        LDR     SP, USR_Stack_Top_Addr

				
        IMPORT	TargetResetInit
        BL		TargetResetInit

; Enter the C code

        IMPORT  __main
        LDR     R0, =__main
        BX      R0

Heap_Bottom_Addr        DCD     Heap_Bottom
USR_Stack_Top_Addr      DCD     USR_Stack_Top
UND_Stack_Top_Addr      DCD     UND_Stack_Top
SVC_Stack_Top_Addr      DCD     SVC_Stack_Top
ABT_Stack_Top_Addr      DCD     ABT_Stack_Top
FIQ_Stack_Top_Addr      DCD     FIQ_Stack_Top
IRQ_Stack_Top_Addr      DCD     IRQ_Stack_Top

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Set Initial User Stack & Heap
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
        AREA    |.text|, CODE, READONLY

; use one region model
        EXPORT  __user_initial_stackheap

__user_initial_stackheap

        LDR     R0, =Heap_Bottom
        LDR     R1, =USR_Stack_Top 
        BX      LR

                END