syslib.c

Tornado的源代码资源包

* This routine initializes various features of the hardware.
* Normally, it is called from usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
/*
*/
    /* install the IRQ/SVC interrupt stack splitting routine */

    _func_armIntStackSplit = sysIntStackSplit;

/*port config*/
   Port_Init();
/*
   Uart_Init(0,115200);
*/   
   
/*   Uart_SendByte('\n');
	for (i=0;i<0xf;i++)	
   		Uart_SendByte('a');
*/   
#ifdef INCLUDE_SERIAL
    /* initialise the serial devices */

    sysSerialHwInit ();      /* initialise serial data structure */
#endif /* INCLUDE_SERIAL */
    }

/*******************************************************************************
*
* sysHwInit2 - additional system configuration and initialization
*
* This routine connects system interrupts and does any additional
* configuration necessary.  Note that this is called from
* sysClkConnect() in the timer driver.
*
* RETURNS: N/A
*
*/

void sysHwInit2 (void)
    {
    static BOOL initialised = FALSE;
	int i;

    if (initialised)
    	return;

/*	Uart_Printf("in sysHwInit2\n");
*/
    /* initialise the interrupt library and interrupt driver */

    intLibInit (S2410_INT_NUM_LEVELS, S2410_INT_NUM_LEVELS, INT_MODE);
    s2410IntDevInit();
	s2410ExcVecSet();

    /* connect sys clock interrupt and auxiliary clock interrupt */

    (void)intConnect (INUM_TO_IVEC (INT_LVL_TICK), sysClkInt,0);
 /*   (void)S2410_intConnect (INUM_TO_IVEC (AUX_TIMER_INT_VEC), sysAuxClkInt, 0);*/
/*
	Uart_Printf("vxIrqIntStackBase=%x  adrs=%x\n",vxIrqIntStackBase,&vxIrqIntStackBase);
	Uart_Printf("vxIrqIntStackEnd=%x  adrs=%x\n",vxIrqIntStackEnd,&vxIrqIntStackEnd);
	Uart_Printf("vxSvcIntStackBase=%x  adrs=%x\n",vxSvcIntStackBase,&vxSvcIntStackBase);
	Uart_Printf("vxSvcIntStackEnd=%x  adrs=%x\n",vxSvcIntStackEnd,&vxSvcIntStackEnd);
*/	

	 for(i=0;i<0x1000;i++);
/*	Uart_Printf("adress 0 = %x\n",  (*(unsigned *)0));
*/
/*	Uart_Printf("rINTMSK  = %x\n",  rINTMSK);
	Uart_Printf("rINTPND  = %x\n",  rINTPND);*/

#ifdef INCLUDE_SERIAL
    /* connect serial interrupt */

    sysSerialHwInit2();
#endif /* INCLUDE_SERIAL */

	
    initialised = TRUE;

    }

/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* Normally, the user specifies the amount of physical memory with the
* macro LOCAL_MEM_SIZE in config.h.  BSPs that support run-time
* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.
* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the
* true size of physical memory.
*
* NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application
* use.  See sysMemTop() for more information on reserving memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/

char * sysPhysMemTop (void)
    {
    static char * physTop = NULL;

    if (physTop == NULL)
	{
#ifdef LOCAL_MEM_AUTOSIZE

        /* If auto-sizing is possible, this would be the spot.  */

#if defined(INCLUDE_MMU)

#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_920T) || defined(CPU_920T_T) || \
    defined(CPU_1020E) || defined(CPU_1022E)
        physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + sysPhysMemDesc[0].len);
#else
	physTop = (char *)(sysPhysMemDesc[1].len);
#endif /* MMU Based CPUs */

#else
	physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);
#endif /* defined(INCLUDE_MMU) */

#else /* LOCAL_MEM_AUTOSIZE */
	/* Don't do autosizing, if size is given */

	physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);

#endif /* LOCAL_MEM_AUTOSIZE */
	}

    return physTop;
    }

/*******************************************************************************
*
* sysMemTop - get the address of the top of VxWorks memory
*
* This routine returns a pointer to the first byte of memory not
* controlled or used by VxWorks.
*
* The user can reserve memory space by defining the macro USER_RESERVED_MEM
* in config.h.  This routine returns the address of the reserved memory
* area.  The value of USER_RESERVED_MEM is in bytes.
*
* RETURNS: The address of the top of VxWorks memory.
*/

char * sysMemTop (void)
    {
    static char * memTop = NULL;

    if (memTop == NULL)
	{
	memTop = sysPhysMemTop () - USER_RESERVED_MEM;
	}

    return memTop;
    }


LOCAL void NAND_load_block0(void);
/*******************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor.  It is usually called
* only by reboot() -- which services ^X -- and bus errors at interrupt
* level.  However, in some circumstances, the user may wish to introduce a
* new <startType> to enable special boot ROM facilities.
*
* RETURNS: Does not return.
*/

STATUS sysToMonitor
    (
    int startType	/* passed to ROM to tell it how to boot */
    )
    {
    FUNCPTR	pRom;
    UINT32 *	p = (UINT32 *)ROM_TEXT_ADRS;

#ifdef INCLUDE_SERIAL
    sysSerialReset ();	/* put serial devices into quiet state */
#endif


#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T)

    VM_ENABLE(FALSE);	/* disable the MMU, cache(s) and write-buffer */
#endif

#if defined(CPU_920T) || defined(CPU_920T_T)
    /*
     * On 920T, can have the I-cache enabled once the MMU has been
     * disabled, so, unlike the other processors, disabling the MMU does
     * not disable the I-cache.  This would not be a problem, as the
     * 920T boot ROM initialisation code disables and flushes both caches.
     * However, in case we are, in fact, using a 7TDMI boot ROM,
     * disable and flush the I-cache here, or else the boot process may
     * fail.
     */

    cacheDisable (INSTRUCTION_CACHE);
#endif /* defined(CPU_920T/920T_T) */

#ifndef NAND_BOOT
    /*
     * Examine ROM - if it's a VxWorks boot ROM, jump to the warm boot entry
     * point; otherwise jump to the start of the ROM.
     * A VxWorks boot ROM begins
     *    MOV	R0,#BOOT_COLD
     *    B	...
     *    DCB	"Copyright"
     * We check the first and third words only. This could be tightened up
     * if required (see romInit.s).
     */

    if (p[0] == 0xE3A00002 && p[2] == 0x79706F43)
	pRom = (FUNCPTR)(ROM_TEXT_ADRS + 4);	/* warm boot address */
    else
	pRom = (FUNCPTR)ROM_TEXT_ADRS;		/* start of ROM */

#else
    pRom = (FUNCPTR)0;

    NAND_load_block0();
    
#endif /* NAND_BOOT */

    (*pRom)(startType);	/* jump to boot ROM */
    return OK;		/* in case we ever continue from ROM monitor */
    }

/****************************************************************************
*
* sysProcNumGet - get the processor number
*
* This routine returns the processor number for the CPU board, which is
* set with sysProcNumSet().
*
* RETURNS: The processor number for the CPU board.
*
* SEE ALSO: sysProcNumSet()
*/

int sysProcNumGet (void)
    {
    return 0;
    }

/****************************************************************************
*
* sysProcNumSet - set the processor number
*
* Set the processor number for the CPU board.  Processor numbers should be
* unique on a single backplane.
*
* NOTE
* By convention, only processor 0 should dual-port its memory.
*
* RETURNS: N/A
*
* SEE ALSO: sysProcNumGet()
*/

void sysProcNumSet
    (
    int procNum		/* processor number */
    )
    {
    sysProcNum = procNum;
    }


#ifdef INCLUDE_FLASH
/******************************************************************************
*
* sysFlashWriteEnable - enable write access to the Flash memory
*
* This routine is used by flashMem.c to enable write access to the
* Flash memory.
*
* RETURNS: N/A
*/

void sysFlashWriteEnable (void)
     {
     volatile UINT32 * ebiCsr = (volatile UINT32 *)INTEGRATOR_EBI_CSR1;

     /* allow write access to EBI_CSR1 area (Flash ) */

     *ebiCsr |= INTEGRATOR_EBI_WRITE_ENABLE;

     if (!(*ebiCsr & INTEGRATOR_EBI_WRITE_ENABLE))
	 {
	 *(volatile UINT32 *)INTEGRATOR_EBI_LOCK = 0xA05F;
	 *ebiCsr |= INTEGRATOR_EBI_WRITE_ENABLE;
	 *(volatile UINT32 *)INTEGRATOR_EBI_LOCK = 0;
	 }

     /* Enable Vpp and allow write access to Flash in system controller */

     *(volatile UINT32 *)INTEGRATOR_SC_CTRLS = FL_SC_CONTROL;
     }

/******************************************************************************
*
* sysFlashWriteDisable - disable write access to the Flash memory
*
* This routine is used by flashMem.c to disable write access to the
* Flash memory.
*
* RETURNS: N/A
*/

void sysFlashWriteDisable (void)
     {
     volatile UINT32 * ebiCsr = (volatile UINT32 *)INTEGRATOR_EBI_CSR1;

     /* disable write access to EBI_CSR1 area (Flash ) */

     *ebiCsr &= ~INTEGRATOR_EBI_WRITE_ENABLE;

     if (*ebiCsr & INTEGRATOR_EBI_WRITE_ENABLE)
	 {
	 *(volatile UINT32 *)INTEGRATOR_EBI_LOCK = 0xA05F;
	 *ebiCsr &= ~INTEGRATOR_EBI_WRITE_ENABLE;
	 *(volatile UINT32 *)INTEGRATOR_EBI_LOCK = 0;
	 }

     /* Disable Vpp and disable write access to Flash in system controller */

     *(volatile UINT32 *)INTEGRATOR_SC_CTRLS = 0;
     }
#endif /* INCLUDE_FLASH */


/*-------------------------------------------------------------------------------------------------*/
#ifdef NAND_BOOT

#define TACLS	0  /*0  //1clk(0ns) */
#define TWRPH0   3  /* 3clk(25ns) */
#define TWRPH1	0 /*0  //1clk(10ns)  //TACLS+TWRPH0+TWRPH1>=50ns*/

#define NF_CMD(cmd)	{rNFCMD=cmd;}
#define NF_ADDR(addr)	{rNFADDR=addr;}	
#define NF_nFCE_L()	{rNFCONF&=~(1<<11);}
#define NF_nFCE_H()	{rNFCONF|=(1<<11);}
#define NF_RSTECC()	{rNFCONF|=(1<<12);}
#define NF_RDDATA() 	(rNFDATA)
#define NF_WRDATA(data) {rNFDATA=data;}

#define NF_WAITRB()    {while(!(rNFSTAT&(1<<0)));} 

LOCAL void sysNF_Reset(void)
{
    int i;
    
    NF_nFCE_L();

    NF_CMD(0xFF);	/*reset command*/

    for(i=0;i<10;i++);  /*tWB = 100ns. //??????*/

    NF_WAITRB();      /*wait 200~500us;*/
     
    NF_nFCE_H();
}


LOCAL void sysNF_Init(void)
{
    rNFCONF=(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);	
    sysNF_Reset();
}


/*------------------------------------------------------------*/
LOCAL int sysNF_ReadPage(UINT32 block,UINT32 page,UCHAR *buffer, UINT32* pageIdx)
{
    int i;
    UINT32 blockPage;
    UCHAR ecc0,ecc1,ecc2;
    UCHAR *bufPt = buffer;
    UCHAR se[16];
    UCHAR * idx = (UCHAR*)pageIdx;   
    
    page=page&0x1f;
    blockPage=(block<<5)+page;
    NF_RSTECC();    /* Initialize ECC*/
    
    NF_nFCE_L();    
    NF_CMD(0x00);   /* Read command*/
    NF_ADDR(0);	    /* Column = 0*/
    NF_ADDR(blockPage&0xff);	    
    NF_ADDR((blockPage>>8)&0xff);   /* Block & Page num.*/
    NF_ADDR((blockPage>>16)&0xff);  

    for(i=0;i<10;i++); /*wait tWB(100ns)/////??????*/
    
    NF_WAITRB();    /* Wait tR(max 12us)*/
    for(i=0;i<512;i++)
    {
    	*bufPt++=NF_RDDATA();	/* Read one page*/
    }
    ecc0=rNFECC0;
    ecc1=rNFECC1;
    ecc2=rNFECC2;
    for(i=0;i<16;i++)
    {
    	se[i]=NF_RDDATA();	/* Read spare array*/
    }
    idx[0] = se[11];
    idx[1] = se[10];
    idx[2] = se[9];
    idx[3] = se[8];
    
    NF_nFCE_H();    

    if(ecc0==se[0] && ecc1==se[1] && ecc2==se[2])
    {
    	return 1;
    }
   	return 0;
}




LOCAL void NAND_load_block0(void)
{
  UCHAR* downPt = 0;
  int i;
  UINT32 pageIdx;

  rINTMSK = BIT_ALLMSK;
  sysNF_Init();

  for(i=0; i<8; i++)   /* Read 8 page. 8*512 bytes*/
  {
    sysNF_ReadPage(0, i, (UCHAR *)downPt, &pageIdx);
    downPt += 512;	    /* Next page*/
  }
}

#endif