syslib.c

Tornado的源代码资源包

    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*
     * Main RAM region from 0 to max(SSRAM,SDRAM), marked cacheable and
     * bufferable. Must always be the second entry.
     */
    {
    (void *) 0,	/* virtual address */
    (void *) 0,	/* physical address */

    /* Region must have alignment equal to size, minimum of PAGE_SIZE */

    ROUND_UP ((LOCAL_MEM_SIZE + LOCAL_MEM_LOCAL_ADRS), PAGE_SIZE), /* length */

    /* initial state: */

    (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE
                        | VM_STATE_MASK_BUFFERABLE) ,
    
    VM_STATE_VALID	| VM_STATE_WRITABLE
    /* 940 errata "do not use write-back memory regions" */
#if defined(CPU_940T)  || defined(CPU_940T_T)
    | VM_STATE_CACHEABLE_WRITETHROUGH
#else
    | VM_STATE_CACHEABLE | VM_STATE_BUFFERABLE
#endif

    },

#if (LOCAL_MEM_LOCAL_ADRS != 0)
    /* If (e.g. on 946ES) we have image starting above where the
     * tightly-coupled memory is, then put another entry (higher priority than
     * the one before), which marks the area taken up by the tightly-coupled
     * memory as non-cacheable.
     */

    /* on-header SSRAM, or tightly-coupled memory */
    {
    (void *) 0,			/* virtual address */
    (void *) 0,			/* physical address */
    ROUND_UP (LOCAL_MEM_LOCAL_ADRS, PAGE_SIZE), /* length, then initial state */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif /* (LOCAL_MEM_LOCAL_ADRS != 0) */

    /*
     * Flash memory: marked valid and writeable but not cached -
     * we need to be able to poll words in the Flash when updating
     * contents.
     */
    {
    (void *) ROM_BASE_ADRS,	/* virtual address */
    (void *) ROM_BASE_ADRS,	/* physical address */

    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),	/* length */

    /* initial state: */

    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* I/O space: */

#ifdef INCLUDE_PCI
    {
    (void *) INTEGRATOR_PCI_BASE,
    (void *) INTEGRATOR_PCI_BASE,
    ROUND_UP (0x20000000, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    (void *) CPU_PCI_IO_ADRS,
    (void *) CPU_PCI_IO_ADRS,
    ROUND_UP (0x4000000, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    }
#endif
    };
#endif /* defined(740T/940T/946ES) */

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);
#endif /* defined(CPU_720T/740T/920T/940T/946ES/1020E/1022E) */

#endif /* defined(INCLUDE_MMU) */

int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */
int	sysCpu	    = CPU;		/* system CPU type (e.g. ARMARCH4/4_T)*/
char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this CPU */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */


unsigned char S2410EnetAddr [6] ={0x00, 0x13, 0xf6, 0x6c, 0x87, 0x89};

/* locals */


/* defines */

/* externals */
extern void excEnterUndef(void);
extern void excEnterSwi(void);
extern void excEnterPrefetchAbort(void);
extern void excEnterDataAbort(void);
extern void intEnt(void);


IMPORT int  s2410IntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);
IMPORT void ASM_sysClkInt();

IMPORT int vxIrqIntStackBase;
IMPORT int vxIrqIntStackEnd;
IMPORT int vxSvcIntStackBase;
IMPORT int vxSvcIntStackEnd;


/* globals */


/* forward LOCAL functions declarations */


/* forward declarations */

char *	sysPhysMemTop (void);


#if defined (INCLUDE_USB)
void sysUsbPciInit(void);
#endif

/* included source files */

#ifdef INCLUDE_FLASH
#include "mem/nvRamToFlash.c"
#include "flashMem.c"
#else
#include "mem/nullNvRam.c"
#endif


#include "vme/nullVme.c"
#include "sysSerial.c"

#include "s3c2410IntrCtl.c"
#include "s3c2410Timer.c"

#ifdef USER_EXTENSIONS
#include "extensions\2410_Pflash_NAND.c"
#include "extensions\k9s1208.c"
#endif
/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* NOTE
* This routine does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/

char *sysModel (void)
    {
#if	defined(CPU_7TDMI)
    return	"ARM Integrator - ARM7TDMI (ARM)";
#elif	defined(CPU_7TDMI_T)
    return	"ARM Integrator - ARM7TDMI (Thumb)";
#elif	defined(CPU_720T)
    return	"ARM Integrator - ARM720T (ARM)";
#elif	defined(CPU_720T_T)
    return	"ARM Integrator - ARM720T (Thumb)";
#elif	defined(CPU_740T)
    return	"ARM Integrator - ARM740T (ARM)";
#elif	defined(CPU_740T_T)
    return	"ARM Integrator - ARM740T (Thumb)";
#elif	defined(CPU_920T)
    return	"SAMSUNG S3C2410A - ARM920T (ARM)";
#elif	defined(CPU_920T_T)
    return	"ARM Integrator - ARM920T (Thumb)";
#elif	defined(CPU_940T)
    return	"ARM Integrator - ARM940T (ARM)";
#elif	defined(CPU_940T_T)
    return	"ARM Integrator - ARM940T (Thumb)";
#elif   defined(CPU_946ES)
    return      "ARM Integrator - ARM946ES (ARM)";
#elif   defined(CPU_946ES_T)
    return      "ARM Integrator - ARM946ES (Thumb)";
#elif   defined(CPU_966ES)
    return      "ARM Integrator - ARM966ES (ARM)";
#elif   defined(CPU_966ES_T)
    return      "ARM Integrator - ARM966ES (Thumb)";
#elif   defined(CPU_1020E)
    return      "ARM Integrator - ARM1020E (ARM)";
#elif   defined(CPU_1022E)
    return      "ARM Integrator - ARM1022E (ARM)";
#else
#error CPU not supported
#endif	/* defined(CPU_7TDMI) */
    }

/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.2/<x>
*
* This function returns a pointer to a BSP version with the revision.
* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_1020E) || defined(CPU_1022E)

/*******************************************************************************
*
* sysHwInit0 - perform early BSP-specific initialisation
*
* This routine performs such BSP-specific initialisation as is necessary before
* the architecture-independent cacheLibInit can be called. It is called
* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS
* has been cleared.
*
* RETURNS: N/A
*/

void sysHwInit0 (void)
    {

#ifdef INCLUDE_CACHE_SUPPORT
    /*
     * Install the appropriate cache library, no address translation
     * routines are required for this BSP, as the default memory map has
     * virtual and physical addresses the same.
     */

#if	defined(CPU_720T) || defined(CPU_720T_T)
    cacheArm720tLibInstall (NULL, NULL);
#elif   defined(CPU_740T) || defined(CPU_740T_T)
    cacheArm740tLibInstall (NULL, NULL);
#elif   defined(CPU_920T) || defined(CPU_920T_T)
    cacheArm920tLibInstall (NULL, NULL);
#elif   defined(CPU_940T) || defined(CPU_940T_T)
    cacheArm940tLibInstall (NULL, NULL);
#elif   defined(CPU_946ES) || defined(CPU_946ES_T)
    cacheArm946eLibInstall (NULL, NULL);
#elif   defined(CPU_1020E)
    cacheArm1020eLibInstall (NULL, NULL);
#elif   defined(CPU_1022E)
    cacheArm1022eLibInstall (NULL, NULL);
#endif
#endif /* INCLUDE_CACHE_SUPPORT */


#if defined(INCLUDE_MMU)

#ifdef LOCAL_MEM_AUTOSIZE
    {
    /* Use the data in the SDRAM control register to set mem size */
    UINT32 ctlSdram;

    ctlSdram = *(UINT32 *)INTEGRATOR_HDR_SDRAM;

    /* Was valid SPD info available when system booted? */
    if( ctlSdram & BIT5 )
        {
        ctlSdram = (ctlSdram >> 2) & 0x7;

        /*
         * ctlSdram now contains the power of two count, starting at
         * 16MB of the size of the DIMM
         */
	ctlSdram = SZ_16M << ctlSdram;

#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_920T) || defined(CPU_920T_T) || \
    defined(CPU_1020E) || defined(CPU_1022E)
        /* Make sure sysPhysMemDesc isn't wrong */
        if( sysPhysMemDesc[0].len == LOCAL_MEM_SIZE)
            sysPhysMemDesc[0].len = ctlSdram + INTEGRATOR_HDR_SSRAM_SIZE;
#else
        /* Make sure sysPhysMemDesc isn't wrong */
        if ( sysPhysMemDesc[1].len == LOCAL_MEM_SIZE + LOCAL_MEM_LOCAL_ADRS)
#if (LOCAL_MEM_LOCAL_ADRS != 0)
            sysPhysMemDesc[1].len = ctlSdram + LOCAL_MEM_LOCAL_ADRS;
#else
            sysPhysMemDesc[1].len = ctlSdram;
#endif /* (LOCAL_MEM_LOCAL_ADRS != 0) */

#endif /* 720T/720T_T/920T/920T_T/1020E/1022E */
        }
    }
#endif /* LOCAL_MEM_AUTOSIZE */
    /* Install the appropriate MMU library and translation routines */

#if	defined(CPU_720T) || defined(CPU_720T_T)
    mmuArm720tLibInstall (NULL, NULL);
#elif   defined(CPU_740T) || defined(CPU_740T_T)
    mmuArm740tLibInstall (NULL, NULL);
#elif   defined(CPU_920T) || defined(CPU_920T_T)
    mmuArm920tLibInstall (NULL, NULL);
#elif   defined(CPU_940T) || defined(CPU_940T_T)
    mmuArm940tLibInstall (NULL, NULL);
#elif   defined(CPU_946ES) || defined(CPU_946ES_T)
    mmuArm946eLibInstall (NULL, NULL);
#elif   defined(CPU_1020E)
    mmuArm1020eLibInstall (NULL, NULL);
#elif   defined(CPU_1022E)
    mmuArm1022eLibInstall (NULL, NULL);
#endif

#endif /* defined(INCLUDE_MMU) */

    return;
    }
#endif /* defined(720T/740T/920T/940T/946ES) */

void s2410ExcVecSet(void)
{
    int i;
    i = (int)&excEnterUndef;
	*((volatile int*)(S2410_EXC_BASE + 0x0)) = i;
	i = (int)&excEnterSwi;
	*((volatile int*)(S2410_EXC_BASE + 0x4)) = i;
	i = (int)&excEnterPrefetchAbort;
	*((volatile int*)(S2410_EXC_BASE + 0x8)) = i;
	i = (int)&excEnterDataAbort;
	*((volatile int*)(S2410_EXC_BASE + 0xc)) = i;
	i = (int)&intEnt;
	*((volatile int*)(S2410_EXC_BASE + 0x14)) = i;
/*
 {
    unsigned int *dst, *src, i;

    dst = 0x100;
    src = 0x31000100;
    for(i=0; i<16; i++)
    {
      *dst = *src;
      dst++;
      src++;
  }

}
 */
	return;
}


/*===========================[ PORTS ]===================================================*/
static void Port_Init(void)
{
    /*CAUTION:Follow the configuration order for setting the ports. */
    /* 1) setting value(GPnDAT) */
    /* 2) setting control register  (GPnCON)*/
    /* 3) configure pull-up resistor(GPnUP)  */

    /*32bit data bus configuration  */
    /*=== PORT A GROUP*/
    /*Ports  : GPA22 GPA21  GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12  */
    /*Signal : nFCE nRSTOUT nFRE   nFWE  ALE   CLE  nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 */
    /*Binary :  1     1      1  , 1   1   1    1   ,  1     1     1     1*/
    /*Ports  : GPA11   GPA10  GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1  GPA0*/
    /*Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 */
    /*Binary :  1       1      1      1   , 1       1      1      1   ,  1       1     1      1        */ 
    rGPACON = 0x7fffff; 

    /*===* PORT B GROUP*/
    /*Ports  : GPB10    GPB9    GPB8    GPB7    GPB6     GPB5    GPB4   GPB3   GPB2     GPB1      GPB0*/
    /*Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard*/
    /*Setting: INPUT  OUTPUT   INPUT  OUTPUT   INPUT   OUTPUT   OUTPUT OUTPUT OUTPUT   OUTPUT    OUTPUT */
    /*Binary :   00  ,  01       00  ,   01      00   ,  01       01  ,   01     01   ,  01        01  */
    rGPBCON = 0x055555;
    rGPBUP  = 0x7ff;     /* The pull up function is disabled GPB[10:0]*/

    /*=== PORT C GROUP*/
    /*Ports  : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8  GPC7   GPC6   GPC5 GPC4 GPC3  GPC2  GPC1 GPC0*/
    /*Signal : VD7   VD6   VD5   VD4   VD3   VD2   VD1  VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND  */
    /*Binary :  10   10  , 10    10  , 10    10  , 10   10  , 10     10  ,  10   10 , 10     10 , 10   10*/
    rGPCCON = 0xaaaaaaaa;       
    rGPCUP  = 0xffff;     /* The pull up function is disabled GPC[15:0] */

    /*=== PORT D GROUP*/
    /*Ports  : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0*/
    /*Signal : VD23  VD22  VD21  VD20  VD19  VD18  VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9  VD8*/
    /*Binary : 10    10  , 10    10  , 10    10  , 10   10 , 10   10 , 10   10 , 10   10 ,10   10*/
    rGPDCON = 0xaaaaaaaa;       
    rGPDUP  = 0xffff;     /* The pull up function is disabled GPD[15:0]*/

    /*=== PORT E GROUP*/
    /*Ports  : GPE15  GPE14 GPE13   GPE12   GPE11   GPE10   GPE9    GPE8     GPE7  GPE6  GPE5   GPE4  */
    /*Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO */
    /*Binary :  10     10  ,  10      10  ,  10      10   ,  10      10   ,   10    10  , 10     10  ,     */
    /*-------------------------------------------------------------------------------------------------------*/
    /*Ports  :  GPE3   GPE2  GPE1    GPE0    */
    /*Signal : I2SSDI CDCLK I2SSCLK I2SLRCK     */
    /*Binary :  10     10  ,  10      10 */
    rGPECON = 0xaaaaaaaa;       
    rGPEUP  = 0xffff;     /* The pull up function is disabled GPE[15:0]*/

    /*=== PORT F GROUP*/
    /*Ports  : GPF7   GPF6   GPF5   GPF4      GPF3     GPF2  GPF1   GPF0*/
    /*Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0*/
    /*Setting: Output Output Output Output    EINT3    EINT2 EINT1  EINT0*/
    /*Binary :  01      01 ,  01     01  ,     10       10  , 10     10*/
    rGPFCON = 0x55aa;
    rGPFUP  = 0xff;     /* The pull up function is disabled GPF[7:0]*/

    /*=== PORT G GROUP*/
    /*Ports  : GPG15 GPG14 GPG13 GPG12 GPG11    GPG10    GPG9     GPG8     GPG7      GPG6    */
    /*Signal : nYPON  YMON nXPON XMON  EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI*/
    /*Setting: nYPON  YMON nXPON XMON  EINT19  Output   Output   Output   SPICLK1    SPIMOSI1*/
    /*Binary :   11    11 , 11    11  , 10      01    ,   01       01   ,    11         11*/
    /*-----------------------------------------------------------------------------------------*/
    /*Ports  :    GPG5       GPG4    GPG3    GPG2    GPG1    GPG0    */
    /*Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA*/
    /*Setting:  SPIMISO1  LCD_PWRDN EINT11   nSS0   EINT9    EINT8*/
    /*Binary :     11         11   ,  10      11  ,  10        10*/
    rGPGCON = 0xff95ffba;
    rGPGUP  = 0xffff;    /* The pull up function is disabled GPG[15:0]*/

/*    
    GPG4 Output Port [9:8] 01      -> LCD_PWREN Enable
    rGPGCON = (rGPGCON & 0xfffffcff) | (1<<8);
    rGPGDAT = (rGPGDAT & 0xffef) | (1<<4);
*/
    /*=== PORT H GROUP*/
    /*Ports  :  GPH10    GPH9  GPH8 GPH7  GPH6  GPH5 GPH4 GPH3 GPH2 GPH1  GPH0 */
    /*Signal : CLKOUT1 CLKOUT0 UCLK nCTS1 nRTS1 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0*/
    /*Binary :   10   ,  10     10 , 11    11  , 10   10 , 10   10 , 10    10*/
    rGPHCON = 0x2afaaa;
    rGPHUP  = 0x7ff;    /* The pull up function is disabled GPH[10:0]*/
    
    /*External interrupt will be falling edge triggered. */
    rEXTINT0 = 0x22222224;    /* EINT[7:0],EINT 0 rising edge trigered*/
    rEXTINT1 = 0x22222222;    /* EINT[15:8]*/
    rEXTINT2 = 0x22222222;    /* EINT[23:16]*/
}

/*******************************************************************************
*
* sysHwInit - initialize the CPU board hardware
*