rominit.s

Tornado的源代码资源包

/* romInit.s - ARM Integrator ROM initialization module */

/* Copyright 1999-2001 ARM Limited */
/* Copyright 1999-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01n,04feb03,jb   Adding ARM10 Support
01m,25jan02,m_h  sdata needs "_" for bootrom_res
01l,09oct01,jpd  added clock speed setting for 946ES.
01k,03oct01,jpd  tidied slightly.
01j,28sep01,pr   added support for ARM946ES.
01i,04jun01,rec  memory clock rate changes for 740t
01h,21feb01,h_k  added support for ARM966ES and ARM966ES_T.
01g,20nov00,jpd  change speeds on 920T and add conditional early
		 enabling of I-cache on 920T.
01f,18sep00,rec  Add delay during power up
01e,23feb00,jpd  comments changes.
01d,22feb00,jpd  changed copyright string.
01c,20jan00,jpd  added support for ARM720T/ARM920T.
01b,13jan00,pr	 added support for ARM740T.
01a,30nov99,ajb  created, based on PID version 01i.
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.  The entry
point, romInit(), is the first code executed on power-up.  It performs
the minimal setup needed to call the generic C routine romStart() with
parameter BOOT_COLD.

romInit() masks interrupts in the processor and the interrupt
controller and sets the initial stack pointer (to STACK_ADRS which is
defined in configAll.h).  Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.

The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot".  This
entry point allows a parameter to be passed to romStart().

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
.I "ARM 7TDMI Data Sheet,"
.
 "ARM 720T Data Sheet,"
.I "ARM 740T Data Sheet,"
.I "ARM 920T Technical Reference Manual",
.I "ARM 940T Technical Reference Manual",
.I "ARM 946E-S Technical Reference Manual",
.I "ARM 966E-S Technical Reference Manual",
.I "ARM 1020E Technical Reference Manual",
.I "ARM 1022E Technical Reference Manual",
.I "ARM Reference Peripherals Specification,"
.I "ARM Integrator/AP User Guide",
.I "ARM Integrator/CM7TDMI User Guide",
.I "ARM Integrator/CM720T User Guide",
.I "ARM Integrator/CM740T User Guide",
.I "ARM Integrator/CM920T User Guide",
.I "ARM Integrator/CM940T User Guide",
.I "ARM Integrator/CM946E User Guide",
.I "ARM Integrator/CM9x6ES Datasheet".
.I "ARM Integrator/CM10200 User Guide",
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "regs.h"	
#include "config.h"
#include "arch/arm/mmuArmLib.h"

        .data
        .globl   VAR(copyright_wind_river)
        .long    VAR(copyright_wind_river)

/* internals */

	.globl	FUNC(romInit)		/* start of system code */
	.globl	VAR(sdata)		/* start of data */
  .globl  _sdata
	.globl	VAR(integratorMemSize)	/* actual memory size */


/* externals */

	.extern	FUNC(romStart)	/* system initialization routine */

	.extern	FUNC(excEnterUndef)        	/* Undefined Instruction routine */
	.extern	FUNC(excEnterSwi)	          /* Software Interrupt routine */
	.extern	FUNC(excEnterPrefetchAbort)	/* Prefetch Abort routine */
	.extern	FUNC(excEnterDataAbort)	    /* Data Abort routine */
	.extern	FUNC(intEnt)	              /* IRQ routine */
	
	.extern VAR(sysExcMsg)

_sdata:
VAR_LABEL(sdata)
	.asciz	"start of data"
	.balign	4

/* variables */

	.data

VAR_LABEL(integratorMemSize)
	.long	0

	.text
	.balign 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit:

      B           cold       	/* reset*/
undefvec:
                B           undefvec        	/* Undefined Instruction*/
/*                ldr pc, L$_excUndef */
swivec:
                B           swivec          	/* Software Interrupt*/
/*                ldr pc, L$_excSwi */
pabtvec:
                B           pabtvec         	/* Prefetch Abort*/
/*                ldr pc, L$_excPrefetchAbort */ 
dabtvec: 
                B           dabtvec         	/* Data Abort*/
/*                ldr pc, L$_excDataAbort */
rsvdvec:
                B           rsvdvec         	/* reserved*/
irqvec:
                B		HandlerIRQ		/* IRQ entry */
/*                ldr pc, L$_IRQV */
fiqvec:
                B           fiqvec          	/* FIQ*/
/*
L$_excUndef:
	.long	FUNC(excEnterUndef)
L$_excSwi:
	.long	FUNC(excEnterSwi)
L$_excPrefetchAbort:
	.long	FUNC(excEnterPrefetchAbort)
L$_excDataAbort:
	.long	FUNC(excEnterDataAbort)
L$_IRQV:
	.long	FUNC(intEnt)
	
L$_sysExcMsg:
  .long sysExcMsg
*/
				
cold:
	MOV	r0, #BOOT_COLD	/* fall through to warm boot entry */
warm:
	B	start

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1999-2001 ARM Limited"
	.ascii   "\nCopyright 1999-2001 Wind River Systems, Inc."
	.balign 4

start:
	/* disable interrupts in CPU and switch to SVC32 mode */

	MRS	r1, cpsr
	BIC	r1, r1, # MASK_MODE/*清除r1寄存器中0-5位*/
	/*5:CPU运行在ARM模式下；
	    4-0:决定运行模式*/
	ORR	r1, r1, # MODE_SVC32 | I_BIT | F_BIT
	/*禁止IRQ和FRQ中断，使CPU工作在管理模式下*/
	MSR	cpsr, r1

	MOV	r13, r0	/* Save starttype in r13 so that r0 can be used for other purposes */

	ldr r1,=0x53000000           /*watch dog disable rWTCON*/
    	ldr r2,=0x0         
    	str r2,[r1]

	ldr r1,=0x4a000008	/*rINTMSK*/
    	ldr r2,=0xffffffff      /*all interrupt disable*/
    	str r2,[r1]

	ldr r1,=0x4a00001c	/*rINTSUBMSK*/
    	ldr r2,=0x7ff           /*all sub interrupt disable*/
    	str r2,[r1]

    	/*To reduce PLL lock time, adjust the LOCKTIME register*/ 
    	ldr r1,=0x4c000000  /*rLOCKTIME*/ 
    	ldr r2,=0xffffff
    	str r2,[r1]

	 /*Configure MPLL*/

	 /*Configure the Clk Divider*/
	ldr r1,=0x4c000014	/*rCLKDIVN*/
	ldr r2,=0x00000003	/*1:2:4*/
	str r2,[r1]

	/*Set Async Bus Mode*/
	mrc  p15,0,r0,c1,c0,0
   	orr  r0,r0,#0xC0000000
   	mcr  p15,0,r0,c1,c0,0

	ldr r1,=0x4c000004      /*rMPLLCON*/ 
   	ldr r2,=0x000a1031 /*Fin=12MHz,Fout=202MHz*/
    	str r2,[r1]	

	
   	/*Set memory control registers*/

	LDR	r1, L$_SystemInitDataSDRAM 
	LDR	r2, L$_SystemInitDataSDRAM + 0x04
	LDR	r3, L$_SystemInitDataSDRAM + 0x08
	LDR	r4, L$_SystemInitDataSDRAM + 0x0c
	LDR	r5, L$_SystemInitDataSDRAM + 0x10
	LDR	r6, L$_SystemInitDataSDRAM + 0x14
	LDR	r7, L$_SystemInitDataSDRAM + 0x18
	LDR	r8, L$_SystemInitDataSDRAM + 0x1c
	LDR	r9, L$_SystemInitDataSDRAM + 0x20
	LDR	r10,L$_SystemInitDataSDRAM + 0x24
	LDR	r11,L$_SystemInitDataSDRAM + 0x28
	LDR	r12,L$_SystemInitDataSDRAM + 0x2c
	LDR	r0, L$_rBWSCON		 /*rBWSCON  Offset 0x48000000*/
	STMIA	r0, {r1-r12}

	LDR r0,L$_rMRSRB7		/*rBWSCON  Offset 0x48000030*/
	LDR	r1,L$_SystemInitDataSDRAM + 0x30
	STR r1,[r0]
	/*
	 * End of DRAM initialisation.*/

	LDR	pc, L$_HiPosn

HiPosn:


	/*LED test*/
	ldr r1,=0x56000010  /*rGPBCON*/
	ldr r2,=0x055555
	str r2,[r1]

	ldr r1,=0x56000018  /*rGPBUP*/
	ldr r2,=0x061f
	str r2,[r1]
/*
test1:	
	ldr r1,=0x56000014
	ldr r2,=0x140
	str r2,[r1]
	
	ldr r3,=0x3ffff
test2:
	subs r3,r3,#1
	bne test2

	ldr r1,=0x56000014
	ldr r2,=0xa0
	str r2,[r1]
*/
	ldr r1,=0x56000014	/*rGPFDAT*/		
	ldr r2,=0xa0
	str r2,[r1]
/*	
	ldr r3,=0x3ffff
test3:
	subs r3,r3,#1
	bne test3
*/
/*	b test1*/

	 
	 /*
	 * Initialize the stack pointer to just before where the
	 * uncompress code, copied from ROM to RAM, will run.
	 */

	LDR	sp, L$_STACK_ADDR
	MOV	fp, #0			/* zero frame pointer */
	MOV	r0, #BOOT_COLD	        /* fall through to warm boot entry */

	/* jump to C entry point in ROM: routine - entry point + ROM base */

#if	(ARM_THUMB)
	LDR	r12, L$_rStrtInRom
	ORR	r12, r12, #1		/* force Thumb state */
	BX	r12
#else
	LDR	pc, L$_rStrtInRom
#endif	/* (ARM_THUMB) */
 

HandlerIRQ:
	 sub sp, sp, #4
	 stmfd sp!, {r0}

	 ldr r0, L$_promIRQ
	 ldr r0, [r0]            
	 str r0, [sp, #4]
	 ldmfd sp!, {r0, pc}


/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor performing substitution
 */

	.balign	4

L$_HiPosn:
	.long	ROM_TEXT_ADRS + HiPosn - FUNC(romInit)

L$_rStrtInRom:
	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L$_STACK_ADDR:
	.long	STACK_ADRS

L$_promIRQ:
	.long     S2410_EXC_BASE + 20


L$_rMRSRB7:
	.long	0x48000030 /*rMRSRB7*/

L$_rBWSCON:
	.long 	0x48000000 /*rBWSCON*/

L$_SystemInitDataSDRAM:
	.long	(0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))	
	.long	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) 	
	.long	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
	.long	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) 
	.long	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
	.long	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) 
	.long	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
	.long	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))	
	.long	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
	.long	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+REFCNT)
	.long	0xb2
	.long	0x30	
	.long	0x30


#if defined(CPU_940T) || defined (CPU_940T_T)

L$_sysCacheUncachedAdrs:
	.long	SYS_CACHE_UNCACHED_ADRS
#endif /* defined(CPU_940T, CPU_940T_T) */