📄 csl_pllhal.h
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/*******************************************************************\
*
* ________________
* | |
* | PLLDIV1 |
* |________________|
*
* PLLDIV1 - "PLL Divider 1 register"
*
* FIELDS (msb -> lsb)
* (rw) D1EN
* (rw) RATIO
*
\*******************************************************************/
#define _PLL_PLLDIV1_OFFSET 70
#define _PLL_PLLDIV1_ADDR (_PLL_BASE_ADDR + 0x118u)
#define PLL_PLLDIV1 PLL_REG(PLLDIV1)
#define _PLL_PLLDIV1_D1EN_MASK 0x00008000u
#define _PLL_PLLDIV1_D1EN_SHIFT 0x0000000Fu
#define PLL_PLLDIV1_D1EN_DEFAULT 0x00000001u
#define PLL_PLLDIV1_D1EN_OF(x) _VALUEOF(x)
#define PLL_PLLDIV1_D1EN_ENABLE 0x00000001u
#define PLL_PLLDIV1_D1EN_DISABLE 0x00000000u
#define _PLL_PLLDIV1_RATIO_MASK 0x0000001Fu
#define _PLL_PLLDIV1_RATIO_SHIFT 0x00000000u
#define PLL_PLLDIV1_RATIO_DEFAULT 0x00000000u
#define PLL_PLLDIV1_RATIO_OF(x) _VALUEOF(x)
/*============= Register DEFAULT macro ==============*/
#define PLL_PLLDIV1_DEFAULT (Uint32) (\
_PER_FDEFAULT(PLL,PLLDIV1,D1EN) \
|_PER_FDEFAULT(PLL,PLLDIV1,RATIO) \
)
/*============= Register MAKE _RMK macro ==============*/
#define PLL_PLLDIV1_RMK(d1en,ratio) \
(Uint32) (\
_PER_FMK(PLL,PLLDIV1,D1EN,d1en) \
|_PER_FMK(PLL,PLLDIV1,RATIO,ratio) \
)
/*============= Register Access macros ==============*/
#define _PLL_PLLDIV1_FGET(FIELD)\
_PER_FGET(_PLL_PLLDIV1_ADDR,PLL,PLLDIV1,##FIELD)
#define _PLL_PLLDIV1_FSET(FIELD,field)\
_PER_FSET(_PLL_PLLDIV1_ADDR,PLL,PLLDIV1,##FIELD,field)
#define _PLL_PLLDIV1_FSETS(FIELD,SYM)\
_PER_FSETS(_PLL_PLLDIV1_ADDR,PLL,PLLDIV1,##FIELD,##SYM)
/*******************************************************************\
*
* ________________
* | |
* | PLLDIV2 |
* |________________|
*
* PLLDIV2 - "PLL Divider 2 register"
*
* FIELDS (msb -> lsb)
* (rw) D2EN
* (rw) RATIO
*
\*******************************************************************/
#define _PLL_PLLDIV2_OFFSET 71
#define _PLL_PLLDIV2_ADDR (_PLL_BASE_ADDR + 0x11Cu)
#define PLL_PLLDIV2 PLL_REG(PLLDIV2)
#define _PLL_PLLDIV2_D2EN_MASK 0x00008000u
#define _PLL_PLLDIV2_D2EN_SHIFT 0x0000000Fu
#define PLL_PLLDIV2_D2EN_DEFAULT 0x00000001u
#define PLL_PLLDIV2_D2EN_OF(x) _VALUEOF(x)
#define PLL_PLLDIV2_D2EN_ENABLE 0x00000001u
#define PLL_PLLDIV2_D2EN_DISABLE 0x00000000u
#define _PLL_PLLDIV2_RATIO_MASK 0x0000001Fu
#define _PLL_PLLDIV2_RATIO_SHIFT 0x00000000u
#define PLL_PLLDIV2_RATIO_DEFAULT 0x00000001u
#define PLL_PLLDIV2_RATIO_OF(x) _VALUEOF(x)
/*============= Register DEFAULT macro ==============*/
#define PLL_PLLDIV2_DEFAULT (Uint32) (\
_PER_FDEFAULT(PLL,PLLDIV2,D2EN) \
|_PER_FDEFAULT(PLL,PLLDIV2,RATIO) \
)
/*============= Register MAKE _RMK macro ==============*/
#define PLL_PLLDIV2_RMK(d2en,ratio) \
(Uint32) (\
_PER_FMK(PLL,PLLDIV2,D2EN,d2en) \
|_PER_FMK(PLL,PLLDIV2,RATIO,ratio) \
)
/*============= Register Access macros ==============*/
#define _PLL_PLLDIV2_FGET(FIELD)\
_PER_FGET(_PLL_PLLDIV2_ADDR,PLL,PLLDIV2,##FIELD)
#define _PLL_PLLDIV2_FSET(FIELD,field)\
_PER_FSET(_PLL_PLLDIV2_ADDR,PLL,PLLDIV2,##FIELD,field)
#define _PLL_PLLDIV2_FSETS(FIELD,SYM)\
_PER_FSETS(_PLL_PLLDIV2_ADDR,PLL,PLLDIV2,##FIELD,##SYM)
/*******************************************************************\
*
* ________________
* | |
* | PLLDIV3 |
* |________________|
*
* PLLDIV3 - "PLL Divider 3 register"
*
* FIELDS (msb -> lsb)
* (rw) D3EN
* (rw) RATIO
*
\*******************************************************************/
#define _PLL_PLLDIV3_OFFSET 72
#define _PLL_PLLDIV3_ADDR (_PLL_BASE_ADDR + 0x120u)
#define PLL_PLLDIV3 PLL_REG(PLLDIV3)
#define _PLL_PLLDIV3_D3EN_MASK 0x00008000u
#define _PLL_PLLDIV3_D3EN_SHIFT 0x0000000Fu
#define PLL_PLLDIV3_D3EN_DEFAULT 0x00000001u
#define PLL_PLLDIV3_D3EN_OF(x) _VALUEOF(x)
#define PLL_PLLDIV3_D3EN_ENABLE 0x00000001u
#define PLL_PLLDIV3_D3EN_DISABLE 0x00000000u
#define _PLL_PLLDIV3_RATIO_MASK 0x0000001Fu
#define _PLL_PLLDIV3_RATIO_SHIFT 0x00000000u
#define PLL_PLLDIV3_RATIO_DEFAULT 0x00000001u
#define PLL_PLLDIV3_RATIO_OF(x) _VALUEOF(x)
/*============= Register DEFAULT macro ==============*/
#define PLL_PLLDIV3_DEFAULT (Uint32) (\
_PER_FDEFAULT(PLL,PLLDIV3,D3EN) \
|_PER_FDEFAULT(PLL,PLLDIV3,RATIO) \
)
/*============= Register MAKE _RMK macro ==============*/
#define PLL_PLLDIV3_RMK(d3en,ratio) \
(Uint32) (\
_PER_FMK(PLL,PLLDIV3,D3EN,d3en) \
|_PER_FMK(PLL,PLLDIV3,RATIO,ratio) \
)
/*============= Register Access macros ==============*/
#define _PLL_PLLDIV3_FGET(FIELD)\
_PER_FGET(_PLL_PLLDIV3_ADDR,PLL,PLLDIV3,##FIELD)
#define _PLL_PLLDIV3_FSET(FIELD,field)\
_PER_FSET(_PLL_PLLDIV3_ADDR,PLL,PLLDIV3,##FIELD,field)
#define _PLL_PLLDIV3_FSETS(FIELD,SYM)\
_PER_FSETS(_PLL_PLLDIV3_ADDR,PLL,PLLDIV3,##FIELD,##SYM)
/*******************************************************************\
*
* ________________
* | |
* | OSCDIV1 |
* |________________|
*
* OSCDIV1 - "Oscillator Divider 1 register"
*
* FIELDS (msb -> lsb)
* (rw) OD1EN
* (rw) RATIO
*
\*******************************************************************/
#define _PLL_OSCDIV1_OFFSET 73
#define _PLL_OSCDIV1_ADDR (_PLL_BASE_ADDR + 0x124u)
#define PLL_OSCDIV1 PLL_REG(OSCDIV1)
#define _PLL_OSCDIV1_OD1EN_MASK 0x00008000u
#define _PLL_OSCDIV1_OD1EN_SHIFT 0x0000000Fu
#define PLL_OSCDIV1_OD1EN_DEFAULT 0x00000001u
#define PLL_OSCDIV1_OD1EN_OF(x) _VALUEOF(x)
#define PLL_OSCDIV1_OD1EN_ENABLE 0x00000001u
#define PLL_OSCDIV1_OD1EN_DISABLE 0x00000000u
#define _PLL_OSCDIV1_RATIO_MASK 0x0000001Fu
#define _PLL_OSCDIV1_RATIO_SHIFT 0x00000000u
#define PLL_OSCDIV1_RATIO_DEFAULT 0x00000007u
#define PLL_OSCDIV1_RATIO_OF(x) _VALUEOF(x)
/*============= Register DEFAULT macro ==============*/
#define PLL_OSCDIV1_DEFAULT (Uint32) (\
_PER_FDEFAULT(PLL,OSCDIV1,OD1EN) \
|_PER_FDEFAULT(PLL,OSCDIV1,RATIO) \
)
/*============= Register MAKE _RMK macro ==============*/
#define PLL_OSCDIV1_RMK(od1en,ratio) \
(Uint32) (\
_PER_FMK(PLL,OSCDIV1,OD1EN,od1en) \
|_PER_FMK(PLL,OSCDIV1,RATIO,ratio) \
)
/*============= Register Access macros ==============*/
#define _PLL_OSCDIV1_FGET(FIELD)\
_PER_FGET(_PLL_OSCDIV1_ADDR,PLL,OSCDIV1,##FIELD)
#define _PLL_OSCDIV1_FSET(FIELD,field)\
_PER_FSET(_PLL_OSCDIV1_ADDR,PLL,OSCDIV1,##FIELD,field)
#define _PLL_OSCDIV1_FSETS(FIELD,SYM)\
_PER_FSETS(_PLL_OSCDIV1_ADDR,PLL,OSCDIV1,##FIELD,##SYM)
/*******************************************************************\
*
* ________________
* | |
* WAKEUP
* |________________|
*
* WAKEUP - "Wakeup register" Not Documented
*
* FIELDS (msb -> lsb)
* (rw) WKEN
*
\*******************************************************************/
#define _PLL_WAKEUP_OFFSET 76
#define _PLL_WAKEUP_ADDR (_PLL_BASE_ADDR + 0x130u)
#define PLL_WAKEUP PLL_REG(WAKEUP)
#define _PLL_WAKEUP_WKEN_MASK 0xFFFFFFFFu
#define _PLL_WAKEUP_WKEN_SHIFT 0x00000000u
#define PLL_WAKEUP_WKEN_DEFAULT 0x00000000u
#define PLL_WAKEUP_WKEN_OF(x) _VALUEOF(x)
#define PLL_WAKEUP_WKEN_ENABLE 0x00000001u
#define PLL_WAKEUP_WKEN_DISABLE 0x00000000u
/*============= Register DEFAULT macro ==============*/
#define PLL_WAKEUP_DEFAULT (Uint32) (\
_PER_FDEFAULT(PLL,WAKEUP,WKEN) \
)
/*============= Register MAKE _RMK macro ==============*/
#define PLL_WAKEUP_RMK(wken) \
(Uint32) (\
_PER_FMK(PLL,WAKEUP,WKEN,wken) \
)
/*============= Register Access macros ==============*/
#define _PLL_WAKEUP_FGET(FIELD)\
_PER_FGET(_PLL_WAKEUP_ADDR,PLL,WAKEUP,##FIELD)
#define _PLL_WAKEUP_FSET(FIELD,field)\
_PER_FSET(_PLL_WAKEUP_ADDR,PLL,WAKEUP,##FIELD,field)
#define _PLL_WAKEUP_FSETS(FIELD,SYM)\
_PER_FSETS(_PLL_WAKEUP_ADDR,PLL,WAKEUP,##FIELD,##SYM)
/*******************************************************************\
*
* ________________
* | |
* CLK3SEL
* |________________|
*
* CLK3SEL - "Clkout3 Select register" Not Documented
*
* FIELDS (msb -> lsb)
* (rw) CK3SEL
*
\*******************************************************************/
#define _PLL_CLK3SEL_OFFSET 65
#define _PLL_CLK3SEL_ADDR (_PLL_BASE_ADDR + 0x104u)
#define PLL_CLK3SEL PLL_REG(CLK3SEL)
#define _PLL_CLK3SEL_CK3SEL_MASK 0x0000000Fu
#define _PLL_CLK3SEL_CK3SEL_SHIFT 0x00000000u
#define PLL_CLK3SEL_CK3SEL_DEFAULT 0x00000000u
#define PLL_CLK3SEL_CK3SEL_OF(x) _VALUEOF(x)
#define PLL_CLK3SEL_CK3SEL_DISABLED 0x00000008u
#define PLL_CLK3SEL_CK3SEL_PTA 0x00000009u
#define PLL_CLK3SEL_CK3SEL_PTB 0x0000000Au
#define PLL_CLK3SEL_CK3SEL_PTC 0x0000000Bu
#define PLL_CLK3SEL_CK3SEL_PTD 0x0000000Cu
#define PLL_CLK3SEL_CK3SEL_PTE 0x0000000Du
#define PLL_CLK3SEL_CK3SEL_PTF 0x0000000Eu
#define PLL_CLK3SEL_CK3SEL_PTG 0x0000000Fu
/*============= Register DEFAULT macro ==============*/
#define PLL_CLK3SEL_DEFAULT (Uint32) (\
_PER_FDEFAULT(PLL,CLK3SEL,CK3SEL) \
)
/*============= Register MAKE _RMK macro ==============*/
#define PLL_CLK3SEL_RMK(ck3sel) \
(Uint32) (\
_PER_FMK(PLL,CLK3SEL,CK3SEL,ck3sel) \
)
/*============= Register Access macros ==============*/
#define _PLL_CLK3SEL_FGET(FIELD)\
_PER_FGET(_PLL_CLK3SEL_ADDR,PLL,CLK3SEL,##FIELD)
#define _PLL_CLK3SEL_FSET(FIELD,field)\
_PER_FSET(_PLL_CLK3SEL_ADDR,PLL,CLK3SEL,##FIELD,field)
#define _PLL_CLK3SEL_FSETS(FIELD,SYM)\
_PER_FSETS(_PLL_CLK3SEL_ADDR,PLL,CLK3SEL,##FIELD,##SYM)
/*----------------------------------------------------------------------*/
#endif /* PLL_SUPPORT */
#endif /* _PLLHAL_H */
/*******************************************************************\
* End of file
\*******************************************************************/
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