clk_3d.tan.rpt

一个1.5分频的VHDL程序,经过编译和仿真.

+-------+--------------+------------+------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To          ; To Clock ;
+-------+--------------+------------+------+-------------+----------+
; N/A   ; None         ; 3.879 ns   ; rst  ; counter2[1] ; clk      ;
; N/A   ; None         ; 3.879 ns   ; rst  ; counter2[0] ; clk      ;
; N/A   ; None         ; 3.744 ns   ; rst  ; tmp2        ; clk      ;
; N/A   ; None         ; 3.535 ns   ; rst  ; counter1[1] ; clk      ;
; N/A   ; None         ; 3.535 ns   ; rst  ; counter1[0] ; clk      ;
; N/A   ; None         ; 3.402 ns   ; rst  ; tmp1        ; clk      ;
+-------+--------------+------------+------+-------------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To      ; From Clock ;
+-------+--------------+------------+------+---------+------------+
; N/A   ; None         ; 6.161 ns   ; tmp1 ; clk_out ; clk        ;
; N/A   ; None         ; 5.371 ns   ; tmp2 ; clk_out ; clk        ;
+-------+--------------+------------+------+---------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; -3.361 ns ; rst  ; tmp1        ; clk      ;
; N/A           ; None        ; -3.494 ns ; rst  ; counter1[1] ; clk      ;
; N/A           ; None        ; -3.494 ns ; rst  ; counter1[0] ; clk      ;
; N/A           ; None        ; -3.703 ns ; rst  ; tmp2        ; clk      ;
; N/A           ; None        ; -3.838 ns ; rst  ; counter2[1] ; clk      ;
; N/A           ; None        ; -3.838 ns ; rst  ; counter2[0] ; clk      ;
+---------------+-------------+-----------+------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Oct 22 13:32:04 2008
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off clk_3d -c clk_3d --speed=6
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "tmp2" and destination register "tmp2"
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.859 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y5_N5; Fanout = 2; REG Node = 'tmp2'
            Info: 2: + IC(0.392 ns) + CELL(0.467 ns) = 0.859 ns; Loc. = LC_X34_Y5_N5; Fanout = 2; REG Node = 'tmp2'
            Info: Total cell delay = 0.467 ns ( 54.37 % )
            Info: Total interconnect delay = 0.392 ns ( 45.63 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.237 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
                Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y5_N5; Fanout = 2; REG Node = 'tmp2'
                Info: Total cell delay = 1.677 ns ( 74.97 % )
                Info: Total interconnect delay = 0.560 ns ( 25.03 % )
            Info: - Longest clock path from clock "clk" to source register is 2.237 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
                Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y5_N5; Fanout = 2; REG Node = 'tmp2'
                Info: Total cell delay = 1.677 ns ( 74.97 % )
                Info: Total interconnect delay = 0.560 ns ( 25.03 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "counter2[1]" (data pin = "rst", clock pin = "clk") is 3.879 ns
    Info: + Longest pin to register delay is 6.087 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_120; Fanout = 6; PIN Node = 'rst'
        Info: 2: + IC(4.285 ns) + CELL(0.667 ns) = 6.087 ns; Loc. = LC_X34_Y5_N6; Fanout = 3; REG Node = 'counter2[1]'
        Info: Total cell delay = 1.802 ns ( 29.60 % )
        Info: Total interconnect delay = 4.285 ns ( 70.40 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.237 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y5_N6; Fanout = 3; REG Node = 'counter2[1]'
        Info: Total cell delay = 1.677 ns ( 74.97 % )
        Info: Total interconnect delay = 0.560 ns ( 25.03 % )
Info: tco from clock "clk" to destination pin "clk_out" through register "tmp1" is 6.161 ns
    Info: + Longest clock path from clock "clk" to source register is 2.237 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'
        Info: Total cell delay = 1.677 ns ( 74.97 % )
        Info: Total interconnect delay = 0.560 ns ( 25.03 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.751 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'
        Info: 2: + IC(0.946 ns) + CELL(0.340 ns) = 1.286 ns; Loc. = LC_X34_Y5_N2; Fanout = 1; COMB Node = 'clk_out~0'
        Info: 3: + IC(0.831 ns) + CELL(1.634 ns) = 3.751 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 1.974 ns ( 52.63 % )
        Info: Total interconnect delay = 1.777 ns ( 47.37 % )
Info: th for register "tmp1" (data pin = "rst", clock pin = "clk") is -3.361 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.237 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'
        Info: Total cell delay = 1.677 ns ( 74.97 % )
        Info: Total interconnect delay = 0.560 ns ( 25.03 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.610 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_120; Fanout = 6; PIN Node = 'rst'
        Info: 2: + IC(3.907 ns) + CELL(0.568 ns) = 5.610 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'
        Info: Total cell delay = 1.703 ns ( 30.36 % )
        Info: Total interconnect delay = 3.907 ns ( 69.64 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 120 megabytes of memory during processing
    Info: Processing ended: Wed Oct 22 13:32:06 2008
    Info: Elapsed time: 00:00:02