prev_cmp_clk_3d.tan.qmsg

一个1.5分频的VHDL程序,经过编译和仿真.

{ "Info" "ITDB_TSU_RESULT" "counter2\[1\] rst clk 3.879 ns register " "Info: tsu for register \"counter2\[1\]\" (data pin = \"rst\", clock pin = \"clk\") is 3.879 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.087 ns + Longest pin register " "Info: + Longest pin to register delay is 6.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns rst 1 PIN PIN_120 6 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_120; Fanout = 6; PIN Node = 'rst'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.285 ns) + CELL(0.667 ns) 6.087 ns counter2\[1\] 2 REG LC_X34_Y5_N6 3 " "Info: 2: + IC(4.285 ns) + CELL(0.667 ns) = 6.087 ns; Loc. = LC_X34_Y5_N6; Fanout = 3; REG Node = 'counter2\[1\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.952 ns" { rst counter2[1] } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns ( 29.60 % ) " "Info: Total cell delay = 1.802 ns ( 29.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.285 ns ( 70.40 % ) " "Info: Total interconnect delay = 4.285 ns ( 70.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.087 ns" { rst counter2[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.087 ns" { rst {} rst~out0 {} counter2[1] {} } { 0.000ns 0.000ns 4.285ns } { 0.000ns 1.135ns 0.667ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.237 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.547 ns) 2.237 ns counter2\[1\] 2 REG LC_X34_Y5_N6 3 " "Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y5_N6; Fanout = 3; REG Node = 'counter2\[1\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.107 ns" { clk counter2[1] } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 74.97 % ) " "Info: Total cell delay = 1.677 ns ( 74.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 25.03 % ) " "Info: Total interconnect delay = 0.560 ns ( 25.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { clk counter2[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.237 ns" { clk {} clk~out0 {} counter2[1] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.087 ns" { rst counter2[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "6.087 ns" { rst {} rst~out0 {} counter2[1] {} } { 0.000ns 0.000ns 4.285ns } { 0.000ns 1.135ns 0.667ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { clk counter2[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.237 ns" { clk {} clk~out0 {} counter2[1] {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_out tmp1 6.161 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_out\" through register \"tmp1\" is 6.161 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.237 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.547 ns) 2.237 ns tmp1 2 REG LC_X34_Y4_N5 2 " "Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.107 ns" { clk tmp1 } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 74.97 % ) " "Info: Total cell delay = 1.677 ns ( 74.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 25.03 % ) " "Info: Total interconnect delay = 0.560 ns ( 25.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { clk tmp1 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.237 ns" { clk {} clk~out0 {} tmp1 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.751 ns + Longest register pin " "Info: + Longest register to pin delay is 3.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp1 1 REG LC_X34_Y4_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp1 } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.340 ns) 1.286 ns clk_out~0 2 COMB LC_X34_Y5_N2 1 " "Info: 2: + IC(0.946 ns) + CELL(0.340 ns) = 1.286 ns; Loc. = LC_X34_Y5_N2; Fanout = 1; COMB Node = 'clk_out~0'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { tmp1 clk_out~0 } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(1.634 ns) 3.751 ns clk_out 3 PIN PIN_135 0 " "Info: 3: + IC(0.831 ns) + CELL(1.634 ns) = 3.751 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.465 ns" { clk_out~0 clk_out } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.974 ns ( 52.63 % ) " "Info: Total cell delay = 1.974 ns ( 52.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.777 ns ( 47.37 % ) " "Info: Total interconnect delay = 1.777 ns ( 47.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.751 ns" { tmp1 clk_out~0 clk_out } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.751 ns" { tmp1 {} clk_out~0 {} clk_out {} } { 0.000ns 0.946ns 0.831ns } { 0.000ns 0.340ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { clk tmp1 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.237 ns" { clk {} clk~out0 {} tmp1 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.751 ns" { tmp1 clk_out~0 clk_out } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.751 ns" { tmp1 {} clk_out~0 {} clk_out {} } { 0.000ns 0.946ns 0.831ns } { 0.000ns 0.340ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "tmp1 rst clk -3.361 ns register " "Info: th for register \"tmp1\" (data pin = \"rst\", clock pin = \"clk\") is -3.361 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.237 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.547 ns) 2.237 ns tmp1 2 REG LC_X34_Y4_N5 2 " "Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.107 ns" { clk tmp1 } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 74.97 % ) " "Info: Total cell delay = 1.677 ns ( 74.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 25.03 % ) " "Info: Total interconnect delay = 0.560 ns ( 25.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { clk tmp1 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.237 ns" { clk {} clk~out0 {} tmp1 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.610 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.610 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns rst 1 PIN PIN_120 6 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_120; Fanout = 6; PIN Node = 'rst'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.907 ns) + CELL(0.568 ns) 5.610 ns tmp1 2 REG LC_X34_Y4_N5 2 " "Info: 2: + IC(3.907 ns) + CELL(0.568 ns) = 5.610 ns; Loc. = LC_X34_Y4_N5; Fanout = 2; REG Node = 'tmp1'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.475 ns" { rst tmp1 } "NODE_NAME" } } { "clk_3d.vhd" "" { Text "D:/clk_3d/clk_3d.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.703 ns ( 30.36 % ) " "Info: Total cell delay = 1.703 ns ( 30.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.907 ns ( 69.64 % ) " "Info: Total interconnect delay = 3.907 ns ( 69.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.610 ns" { rst tmp1 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.610 ns" { rst {} rst~out0 {} tmp1 {} } { 0.000ns 0.000ns 3.907ns } { 0.000ns 1.135ns 0.568ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { clk tmp1 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.237 ns" { clk {} clk~out0 {} tmp1 {} } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.610 ns" { rst tmp1 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.610 ns" { rst {} rst~out0 {} tmp1 {} } { 0.000ns 0.000ns 3.907ns } { 0.000ns 1.135ns 0.568ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 22 13:29:39 2008 " "Info: Processing ended: Wed Oct 22 13:29:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}