clk_3d.hier_info

一个1.5分频的VHDL程序,经过编译和仿真.

|clk_3d
clk => counter1[1].CLK
clk => counter1[0].CLK
clk => tmp1.CLK
clk => counter2[1].CLK
clk => counter2[0].CLK
clk => tmp2.CLK
rst => tmp2.ENA
rst => tmp1.ENA
rst => counter1[1].ENA
rst => counter1[0].ENA
rst => counter2[1].ENA
rst => counter2[0].ENA
clk_out <= clk_out~0.DB_MAX_OUTPUT_PORT_TYPE