cd.tan.rpt

来自「一个彩灯循环控制的VHDL程序,功能还可添加.」· RPT 代码 · 共 312 行 · 第 1/3 页

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Nov 04 20:11:34 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cd -c cd --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "jishu2[0]" is a latch
    Warning: Node "jishu2[1]" is a latch
    Warning: Node "jishu2[2]" is a latch
    Warning: Node "dout_tmp[0]" is a latch
    Warning: Node "dout_tmp[1]" is a latch
    Warning: Node "dout_tmp[2]" is a latch
    Warning: Node "dout_tmp[3]" is a latch
    Warning: Node "dout_tmp[4]" is a latch
    Warning: Node "dout_tmp[5]" is a latch
    Warning: Node "dout_tmp[6]" is a latch
    Warning: Node "dout_tmp[7]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "jishu2[2]" as buffer
    Info: Detected ripple clock "jishu2[1]" as buffer
    Info: Detected ripple clock "jishu2[0]" as buffer
    Info: Detected gated clock "Mux8~230" as buffer
    Info: Detected gated clock "Mux8~229" as buffer
    Info: Detected gated clock "Mux8~228" as buffer
    Info: Detected gated clock "dout_tmp[2]~1564" as buffer
    Info: Detected ripple clock "jishu1[4]" as buffer
    Info: Detected ripple clock "jishu1[3]" as buffer
    Info: Detected ripple clock "jishu1[5]" as buffer
Info: Clock "clk" has Internal fmax of 298.86 MHz between source register "jishu1[2]" and destination register "jishu1[5]" (period= 3.346 ns)
    Info: + Longest register to register delay is 3.144 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y16_N7; Fanout = 28; REG Node = 'jishu1[2]'
        Info: 2: + IC(1.288 ns) + CELL(0.454 ns) = 1.742 ns; Loc. = LC_X8_Y17_N1; Fanout = 2; COMB Node = 'Equal0~666'
        Info: 3: + IC(0.935 ns) + CELL(0.467 ns) = 3.144 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1[5]'
        Info: Total cell delay = 0.921 ns ( 29.29 % )
        Info: Total interconnect delay = 2.223 ns ( 70.71 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.272 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.595 ns) + CELL(0.547 ns) = 2.272 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1[5]'
            Info: Total cell delay = 1.677 ns ( 73.81 % )
            Info: Total interconnect delay = 0.595 ns ( 26.19 % )
        Info: - Longest clock path from clock "clk" to source register is 2.272 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.595 ns) + CELL(0.547 ns) = 2.272 ns; Loc. = LC_X9_Y16_N7; Fanout = 28; REG Node = 'jishu1[2]'
            Info: Total cell delay = 1.677 ns ( 73.81 % )
            Info: Total interconnect delay = 0.595 ns ( 26.19 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Warning: Circuit may not operate. Detected 48 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "jishu1[1]" and destination pin or register "dout_tmp[5]" for clock "clk" (Hold time is 4.27 ns)
    Info: + Largest clock skew is 6.205 ns
        Info: + Longest clock path from clock "clk" to destination register is 8.477 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.595 ns) + CELL(0.720 ns) = 2.445 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1[5]'
            Info: 3: + IC(1.015 ns) + CELL(0.340 ns) = 3.800 ns; Loc. = LC_X8_Y14_N9; Fanout = 3; COMB Node = 'dout_tmp[2]~1564'
            Info: 4: + IC(0.558 ns) + CELL(0.340 ns) = 4.698 ns; Loc. = LC_X7_Y14_N4; Fanout = 8; COMB Node = 'Mux8~230'
            Info: 5: + IC(3.554 ns) + CELL(0.225 ns) = 8.477 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp[5]'
            Info: Total cell delay = 2.755 ns ( 32.50 % )
            Info: Total interconnect delay = 5.722 ns ( 67.50 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.272 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.595 ns) + CELL(0.547 ns) = 2.272 ns; Loc. = LC_X9_Y16_N9; Fanout = 39; REG Node = 'jishu1[1]'
            Info: Total cell delay = 1.677 ns ( 73.81 % )
            Info: Total interconnect delay = 0.595 ns ( 26.19 % )
    Info: - Micro clock to output delay of source is 0.173 ns
    Info: - Shortest register to register delay is 1.762 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y16_N9; Fanout = 39; REG Node = 'jishu1[1]'
        Info: 2: + IC(0.437 ns) + CELL(0.225 ns) = 0.662 ns; Loc. = LC_X9_Y16_N6; Fanout = 1; COMB Node = 'dout_tmp[5]~1576'
        Info: 3: + IC(0.328 ns) + CELL(0.088 ns) = 1.078 ns; Loc. = LC_X9_Y16_N0; Fanout = 1; COMB Node = 'Mux2~220'
        Info: 4: + IC(0.140 ns) + CELL(0.088 ns) = 1.306 ns; Loc. = LC_X9_Y16_N1; Fanout = 1; COMB Node = 'Mux2~221'
        Info: 5: + IC(0.140 ns) + CELL(0.088 ns) = 1.534 ns; Loc. = LC_X9_Y16_N2; Fanout = 1; COMB Node = 'Mux2~223'
        Info: 6: + IC(0.140 ns) + CELL(0.088 ns) = 1.762 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp[5]'
        Info: Total cell delay = 0.577 ns ( 32.75 % )
        Info: Total interconnect delay = 1.185 ns ( 67.25 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: tco from clock "clk" to destination pin "dout[5]" through register "dout_tmp[5]" is 11.692 ns
    Info: + Longest clock path from clock "clk" to source register is 8.477 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.595 ns) + CELL(0.720 ns) = 2.445 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1[5]'
        Info: 3: + IC(1.015 ns) + CELL(0.340 ns) = 3.800 ns; Loc. = LC_X8_Y14_N9; Fanout = 3; COMB Node = 'dout_tmp[2]~1564'
        Info: 4: + IC(0.558 ns) + CELL(0.340 ns) = 4.698 ns; Loc. = LC_X7_Y14_N4; Fanout = 8; COMB Node = 'Mux8~230'
        Info: 5: + IC(3.554 ns) + CELL(0.225 ns) = 8.477 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp[5]'
        Info: Total cell delay = 2.755 ns ( 32.50 % )
        Info: Total interconnect delay = 5.722 ns ( 67.50 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 3.215 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp[5]'
        Info: 2: + IC(1.593 ns) + CELL(1.622 ns) = 3.215 ns; Loc. = PIN_226; Fanout = 0; PIN Node = 'dout[5]'
        Info: Total cell delay = 1.622 ns ( 50.45 % )
        Info: Total interconnect delay = 1.593 ns ( 49.55 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 15 warnings
    Info: Allocated 115 megabytes of memory during processing
    Info: Processing ended: Tue Nov 04 20:11:35 2008
    Info: Elapsed time: 00:00:01