prev_cmp_cd.map.qmsg

一个彩灯循环控制的VHDL程序,功能还可添加.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 04 20:09:54 2008 " "Info: Processing started: Tue Nov 04 20:09:54 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cd -c cd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cd -c cd" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "cd.vhd 2 1 " "Warning: Using design file cd.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cd-m " "Info: Found design unit 1: cd-m" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cd " "Info: Found entity 1: cd" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cd " "Info: Elaborating entity \"cd\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_EXPR_HAS_WRONG_NUM_OF_ELEMENTS" "\"000000\" 6 7 cd.vhd(18) " "Error (10324): VHDL Expression error at cd.vhd(18): expression \"\"000000\"\" has 6 elements ; expected 7 elements." {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 18 0 0 } }  } 0 10324 "VHDL Expression error at %4!s!: expression \"%1!s!\" has %2!d! elements ; expected %3!d! elements." 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Allocated 156 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Tue Nov 04 20:09:56 2008 " "Error: Processing ended: Tue Nov 04 20:09:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}