memory.s

pxa255,bootloaer ,从初始化中断到GPIO口

;/*MDCNFG SDRAM Configuration Register 0x48000000 */	
DE0			EQU			(0x1<<0)
DE1			EQU			(0x0<<1)
DWID0		EQU			(0x0<<2)
DCAC0		EQU			(0x1<<3)
DRAC0		EQU			(0x2<<5)
DNB0		EQU			(0x1<<7)
DTC0		EQU			(0x2<<8)
DADDR0		EQU			(0x0<<10)
DLATCH0		EQU			(0x1<<11)
DSA1111_0	EQU			(0x1<<12)
DE2			EQU			(0x0<<16)
DE3			EQU			(0x0<<17)
DWID2		EQU			(0x0<<18)
DCAC2		EQU			(0x0<<19)
DRAC2		EQU			(0x0<<21)
DNB2		EQU			(0x0<<23)
DTC2		EQU			(0x0<<24)
DADDR2		EQU			(0x0<<26)
DLATCH2		EQU			(0x0<<27)
DSA1111_2	EQU			(0x0<<28)

;/*MDREFR SDRAM Refresh Control Register 0x48000004 */
DRI			EQU			(0x018<<0)
E0PIN		EQU			(0x0<<12)
K0RUN		EQU			(0x0<<13)
K0DB2		EQU			(0x1<<14)
E1PIN		EQU			(0x1<<15)
K1RUN		EQU			(0x1<<16)
K1DB2		EQU			(0x0<<17)
K2RUN		EQU			(0x0<<18)
K2DB2		EQU			(0x1<<19)
APD			EQU			(0x0<<20)
SLFRSH		EQU			(0x0<<22)
K0FREE		EQU			(0x1<<23)
K1FREE		EQU			(0x1<<24)
K2FREE		EQU			(0x1<<25)

;/*MSC0 Static Memory Control Register 0 0x48000008 */
MSC0_RT0_2_4	EQU			(0x0<<0)
MSC0_RBW0_2_4	EQU			(0x1<<3)
MSC0_RDF0_2_4	EQU			(0xc<<4)
MSC0_RDN0_2_4	EQU			(0xc<<8)
MSC0_RRR0_2_4	EQU			(0x7<<12)
MSC0_RBUFF0_2_4	EQU			(0x0<<15)
MSC0_RT1_3_5	EQU			(0x0<<16)
MSC0_RBW1_3_5	EQU			(0x1<<19)
MSC0_RDF1_3_5	EQU			(0xc<<20)
MSC0_RDN1_3_5	EQU			(0xc<<24)
MSC0_RRR1_3_5	EQU			(0x7<<28)
MSC0_RBUFF1_3_5	EQU			(0x0<<31)

;/*MSC1 Static Memory Control Register 0 0x4800000c */
MSC1_RT0_2_4	EQU			(0x0<<0)
MSC1_RBW0_2_4	EQU			(0x0<<3)
MSC1_RDF0_2_4	EQU			(0xf<<4)
MSC1_RDN0_2_4	EQU			(0xf<<8)
MSC1_RRR0_2_4	EQU			(0x7<<12)
MSC1_RBUFF0_2_4	EQU			(0x0<<15)
MSC1_RT1_3_5	EQU			(0x0<<16)
MSC1_RBW1_3_5	EQU			(0x0<<19)
MSC1_RDF1_3_5	EQU			(0xf<<20)
MSC1_RDN1_3_5	EQU			(0xf<<24)
MSC1_RRR1_3_5	EQU			(0x7<<28)
MSC1_RBUFF1_3_5	EQU			(0x0<<31)

;/*MSC2 Static Memory Control Register 0 0x48000010 */
MSC2_RT0_2_4	EQU			(0x0<<0)
MSC2_RBW0_2_4	EQU			(0x0<<3)
MSC2_RDF0_2_4	EQU			(0xf<<4)
MSC2_RDN0_2_4	EQU			(0xf<<8)
MSC2_RRR0_2_4	EQU			(0x7<<12)
MSC2_RBUFF0_2_4	EQU			(0x0<<15)
MSC2_RT1_3_5	EQU			(0x0<<16)
MSC2_RBW1_3_5	EQU			(0x0<<19)
MSC2_RDF1_3_5	EQU			(0xf<<20)
MSC2_RDN1_3_5	EQU			(0xf<<24)
MSC2_RRR1_3_5	EQU			(0x7<<28)
MSC2_RBUFF1_3_5	EQU			(0x0<<31)

;/*MECR Expansion Memory (PCMCIA/Compact Flash Bus Configuration 0x48000014 */
NOS			EQU			(0x0<<0)
CIT			EQU			(0x0<<1)

;/*SXLCR LCR value to be written to SDRAM-Timing Synchronous Flash 0x48000018 */


;/*SXCNFG Synchronous Static Memory Control Register 0x4800001c */
SXEN0		EQU			(0x0<<0)
SXCL0		EQU			(0x5<<2)
SXRL0		EQU			(0x7<<5)
SXRA0		EQU			(0x0<<8)
SXCA0		EQU			(0x0<<10)
SXTP0		EQU			(0x2<<12)
SXLATCH0	EQU			(0x1<<14)
SXEN2		EQU			(0x0<<16)
SXCL2		EQU			(0x0<<18)
SXRL2		EQU			(0x0<<21)
SXRA2		EQU			(0x0<<24)
SXCA2		EQU			(0x0<<26)
SXTP2		EQU			(0x0<<28)
SXLATCH2	EQU			(0x0<<30)

;/* SXMRS MRS value to be written to Synchronous Flash or SMROM 0x48000024 */

SXMRS0		EQU			(0x0232<<0)
SXMRS2		EQU			(0x0232<<16)

;/*MCMEM0 Card interface Common Memory Space Socket 0 Timing 0x48000028 */
MEM0_SET	EQU			(0x0<<0)
MEM0_ASST	EQU			(0x0<<7)
MEM0_HOLD	EQU			(0x0<<14)

;/*MCMEM1 Card interface Common Memory Space Socket 1 Timing 0x4800002c */
MEM1_SET	EQU			(0x0<<0)
MEM1_ASST	EQU			(0x0<<7)
MEM1_HOLD	EQU			(0x0<<14)

;/*MCATT0 Card interface Attribute Space Socket 0 Timing Configuration 0x48000030 */
ATT0_SET	EQU			(0x0<<0)
ATT0_ASST	EQU			(0x0<<7)
ATT0_HOLD	EQU			(0x0<<14)

;/*MCATT1 Card interface Attribute Space Socket 1 Timing Configuration 0x48000034 */
ATT1_SET	EQU			(0x0<<0)
ATT1_ASST	EQU			(0x0<<7)
ATT1_HOLD	EQU			(0x0<<14)

;/*MCIO0 Card interface I/O Space Socket 0 Timing Configuration 0x48000038 */
IO0_SET		EQU			(0x0<<0)
IO0_ASST	EQU			(0x0<<7)
IO0_HOLD	EQU			(0x0<<14)

;/*MCIO1 Card interface I/O Space Socket 1 Timing Configuration 0x4800003c */
IO1_SET		EQU			(0x0<<0)
IO1_ASST	EQU			(0x0<<7)
IO1_HOLD	EQU			(0x0<<14)	

;/*MDMRS MRS value to be written to SDRAM 0x48000040 */
MDBL0		EQU			(0x0<<0)
MDADD0		EQU			(0x0<<3)
MDCL0		EQU			(0x0<<4)
MDMRS0		EQU			(0x0<<7)
MDBL2		EQU			(0x0<<16)
MDADD2		EQU			(0x0<<19)
MDCL2		EQU			(0x0<<20)
MDMRS2		EQU			(0x0<<23)

;/*BOOT_DEF Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL 0x48000044 */

;/*MDMRSLP  0x48000058*/
MDMRSLP0	EQU			(0x0<<0)
MDLPEN0		EQU			(0x0<<15)
MDMRSLP2	EQU			(0x0<<16)
MDLPEN2		EQU			(0x0<<31)


			END