📄 register.s
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IM8 EQU (0x0<<8) ;if IM[x]=0x0 Pending interrupt is masked from becoming active (interrupts are NOT sent to CPU or Power Manager)
IM9 EQU (0x0<<9) ;if IM[x]=0x1 Pending interrupt is allowed to become active (interrupts are sent to CPU and Power Manager)
IM10 EQU (0x0<<10)
IM11 EQU (0x0<<11)
IM12 EQU (0x0<<12)
IM13 EQU (0x0<<13)
IM14 EQU (0x0<<14)
IM17 EQU (0x0<<17)
IM18 EQU (0x0<<18)
IM19 EQU (0x0<<19)
IM20 EQU (0x0<<20)
IM21 EQU (0x0<<21)
IM22 EQU (0x0<<22)
IM23 EQU (0x0<<23)
IM24 EQU (0x0<<24)
IM25 EQU (0x0<<25)
IM26 EQU (0x0<<26)
IM27 EQU (0x0<<27)
IM28 EQU (0x0<<28)
IM29 EQU (0x0<<29)
IM30 EQU (0x0<<30)
IM31 EQU (0x0<<31)
ICMR_Value EQU (IM8|IM9|IM10|IM11|IM12|IM13|IM14|IM17|IM18|IM19|IM20|IM21|IM22|IM23|IM24|IM25|IM26|IM27|IM28|IM29|IM30|IM31)
ICLR EQU 0x40d00008 ;//Interrupt Controller Level Register
IL8 EQU (0x0<<8) ;if IL[x]=0x0,Interrupt routed to IRQ interrupt input.
IL9 EQU (0x0<<9) ;if IL[x]=0x1,Interrupt routed to FIQ interrupt input.
IL10 EQU (0x0<<10)
IL11 EQU (0x0<<11)
IL12 EQU (0x0<<12)
IL13 EQU (0x0<<13)
IL14 EQU (0x0<<14)
IL17 EQU (0x0<<17)
IL18 EQU (0x0<<18)
IL19 EQU (0x0<<19)
IL20 EQU (0x0<<20)
IL21 EQU (0x0<<21)
IL22 EQU (0x0<<22)
IL23 EQU (0x0<<23)
IL24 EQU (0x0<<24)
IL25 EQU (0x0<<25)
IL26 EQU (0x0<<26)
IL27 EQU (0x0<<27)
IL28 EQU (0x0<<28)
IL29 EQU (0x0<<29)
IL30 EQU (0x0<<30)
IL31 EQU (0x0<<31)
ICLR_Value EQU (IL8|IL9|IL10|IL11|IL12|IL13|IL14|IL17|IL18|IL19|IL20|IL21|IL22|IL23|IL24|IL25|IL26|IL27|IL28|IL29|IL30|IL31)
ICFP EQU 0x40d0000c ;//Interrupt Controller FIQ Pending Register
FP8 EQU (0x0<<8)
FP9 EQU (0x0<<9)
FP10 EQU (0x0<<10)
FP11 EQU (0x0<<11)
FP12 EQU (0x0<<12)
FP13 EQU (0x0<<13)
FP14 EQU (0x0<<14)
FP17 EQU (0x0<<17)
FP18 EQU (0x0<<18)
FP19 EQU (0x0<<19)
FP20 EQU (0x0<<20)
FP21 EQU (0x0<<21)
FP22 EQU (0x0<<22)
FP23 EQU (0x0<<23)
FP24 EQU (0x0<<24)
FP25 EQU (0x0<<25)
FP26 EQU (0x0<<26)
FP27 EQU (0x0<<27)
FP28 EQU (0x0<<28)
FP29 EQU (0x0<<29)
FP30 EQU (0x0<<30)
FP31 EQU (0x0<<31)
ICFP_Value EQU (FP8|FP9|FP10|FP11|FP12|FP13|FP14|FP17|FP18|FP19|FP20|FP21|FP22|FP23|FP24|FP25|FP26|FP27|FP28|FP29|FP30|FP31)
ICPR EQU 0x40d00010 ;//Interrupt Controller Pending Regis if IS[x]=0x0,NOT pending if IS[x]=0x1,pending
IS8 EQU (0x0<<8) ;GPIO[0] Edge Detect Interrupt Pending
IS9 EQU (0x0<<9) ;GPIO[1] Edge Detect Interrupt Pending
IS10 EQU (0x0<<10) ;GPIO[80:2] Edge Detect Interrupt Pending
IS11 EQU (0x0<<11) ;USB Service Interrupt Pending
IS12 EQU (0x0<<12) ;Performance Monitoring Unit (PMU) Interrupt Pending
IS13 EQU (0x0<<13) ;I2S Interrupt Pending
IS14 EQU (0x0<<14) ;AC97 Interrupt Pending
IS17 EQU (0x0<<17) ;LCD Controller Service Request Interrupt Pending
IS18 EQU (0x0<<18) ;I2C Service Request Interrupt Pending
IS19 EQU (0x0<<19) ;ICP Transmit/Receive/Error Interrupt Pending
IS20 EQU (0x0<<20) ;STUART Transmit/Receive/Error Interrupt Pending
IS21 EQU (0x0<<21) ;BTUART Transmit/Receive/Error Interrupt Pending
IS22 EQU (0x0<<22) ;FFUART Transmit/Receive/Error Interrupt Pending
IS23 EQU (0x0<<23) ;MMC Status/Error Detection Interrupt Pending
IS24 EQU (0x0<<24) ;SSP Service Request Interrupt Pending
IS25 EQU (0x0<<25) ;DMA Channel Service Request Interrupt Pending
IS26 EQU (0x0<<26) ;OS Timer Match Register 0 Interrupt Pending
IS27 EQU (0x0<<27) ;OS Timer Match Register 1 Interrupt Pending
IS28 EQU (0x0<<28) ;OS Timer Match Register 2 Interrupt Pending
IS29 EQU (0x0<<29) ;OS Timer Match Register 3 Interrupt Pending
IS30 EQU (0x0<<30) ;RTC HZ Clock Tick Interrupt Pending
IS31 EQU (0x0<<31) ;RTC Alarm Match Register Interrupt Pending
ICPR_Value EQU (IS8|IS9|IS10|IS11|IS12|IS13|IS14|IS17|IS18|IS19|IS20|IS21|IS22|IS23|IS24|IS25|IS26|IS27|IS28|IS29|IS30|IS31)
ICCR EQU 0x40d00014 ;//Interrupt Controller Control Register
;//if DIM=0x1 Only enabled and unmasked (as defined in the ICMR) bring the processor out of idle mode.
DIM EQU (0x0<<0) ;//if DIM=0x0 All enabled interrupts bring the processor out of idle mode.
ICCR_Value EQU (DIM)
;/*************************************************************
;*****************Real-Time Clock Register*********************
;*************************************************************/
RCNR EQU 0xe0900000 ;//RTC Counter Register
RCNR_Value EQU 0x00000000
RTAR EQU 0x40900004 ;//RTC Alarm Register
RTAR_Value EQU 0x00000000
RTSR EQU 0x40900008 ;//RTC Status Register
AL EQU (0x0<<0) ;RTC alarm detected.
HZ EQU (0x0<<1) ;HZ rising-edge detected.
ALE EQU (0x0<<2) ;RTC alarm interrupt enable.
HZE EQU (0x0<<3) ;HZ interrupt enable.
RTSR_Value EQU (AL+HZ+ALE+HZE)
RTTR EQU 0x4090000c ;//RTC Trim Register
CKDIV0 EQU (0x1<<0) ;Clock divider count.
CKDIV1 EQU (0x1<<1) ;/*This value is the number
CKDIV2 EQU (0x1<<2) ; of 32 kHz clock cycles,
CKDIV3 EQU (0x1<<3) ; plus 1, per HZ clock cycle.*/
CKDIV4 EQU (0x1<<4)
CKDIV5 EQU (0x1<<5)
CKDIV6 EQU (0x1<<6)
CKDIV7 EQU (0x1<<7)
CKDIV8 EQU (0x1<<8)
CKDIV9 EQU (0x1<<9)
CKDIV10 EQU (0x1<<10)
CKDIV11 EQU (0x1<<11)
CKDIV12 EQU (0x1<<12)
CKDIV13 EQU (0x1<<13)
CKDIV14 EQU (0x1<<14)
CKDIV15 EQU (0x0<<15)
DEL16 EQU (0x0<<16) ; Trim delete count.
DEL17 EQU (0x0<<17) ;/* This value represents
DEL18 EQU (0x0<<18) ; the number of 32 kHz
DEL19 EQU (0x0<<19) ; clocks to delete when
DEL20 EQU (0x0<<20) ; clock trimming begins.*/
DEL21 EQU (0x0<<21)
DEL22 EQU (0x0<<22)
DEL23 EQU (0x0<<23)
DEL24 EQU (0x0<<24)
DEL25 EQU (0x0<<25)
LCK EQU (0x0<<31) ;Locking bit for the trim value.
;if LCK=0x0,allowed to be altered.
;if LCK=0x1,not allowed to be altered.
RTTR_Value EQU (CKDIV0|CKDIV1|CKDIV2|CKDIV3|CKDIV4|CKDIV5|CKDIV6|CKDIV7|CKDIV8|CKDIV9|CKDIV10|CKDIV11|CKDIV12|CKDIV13|CKDIV14|CKDIV15|DEL16|DEL17|DEL18|DEL19|DEL20|DEL21|DEL22|DEL23|DEL24|DEL25|LCK)
;/*************************************************************
;*****************OS Timer Register****************************
;*************************************************************/
OSMR0 EQU 0x40a00000 ;//OS Timer Match Register 0
OSMR0_Value EQU 0x00000000
OSMR1 EQU 0x40a00004 ;//OS Timer Match Register 1
OSMR1_Value EQU 0x00000000
OSMR2 EQU 0x40a00008 ;//OS Timer Match Register 2
OSMR2_Value EQU 0x00000000
OSMR3 EQU 0x40a0000c ;//OS Timer Match Register 3
OSMR3_Value EQU 0x00000000
OSCR EQU 0x40a00010 ;//OS Timer Count Register
OSCR_Value EQU 0x00000000
OSSR EQU 0x40a00014 ;//OS Timer Status Register
M0 EQU (0x0<<0)
M1 EQU (0x0<<1)
M2 EQU (0x0<<2)
M3 EQU (0x0<<3)
OSSR_Value EQU (M0+M1+M2+M3)
OWER EQU 0x40a00018 ;//Timer Watchdog Match Enable Register
OWER_Value EQU 0x00000000 ;if is 0 OSMR3 not reset processer
;if is 1 OSMR3 reset processer
OIER EQU 0x40a0001c ;//OS Timer Interrupt Enable Register
E0 EQU (0x0<<0)
E1 EQU (0x0<<1)
E2 EQU (0x0<<2)
E3 EQU (0x0<<3)
OIER_Value EQU (E0+E1+E2+E3)
;/**********************************************
;**************Pulse Width Modulator***********
;**********************************************/
PWM_CTRL0 EQU 0x40b00000 ;//PWM Control Registers 0
PRESCALE00 EQU (0x0<<0)
PRESCALE01 EQU (0x0<<1) ;PWMn Prescale Divisor.
PRESCALE02 EQU (0x0<<2) ;Determines the frequency of the PWM module clock (in terms of the 3.86 MHz clock)
PRESCALE03 EQU (0x0<<3) ;PSCLK_PWMn = 3.6864 MHz / (PWM_CTRL[PRESCALE] + 1)
PRESCALE04 EQU (0x0<<4)
PRESCALE05 EQU (0x0<<5)
PWM_SD0 EQU (0x0<<6) ;if pwm_sd=0x0 Graceful shutdown. if pwm_sd=0x1 Abrupt shutdown
PWM_CTRL0_Value EQU (PRESCALE00|PRESCALE01|PRESCALE02|PRESCALE03|PRESCALE04|PRESCALE05|PWM_SD0)
PWM_DUTY0 EQU 0x40b00004 ;//PWM Duty Cycle Registers0
DCYCLE00 EQU (0x0<<0)
DCYCLE01 EQU (0x0<<1) ;
DCYCLE02 EQU (0x0<<2)
DCYCLE03 EQU (0x0<<3)
DCYCLE04 EQU (0x0<<4)
DCYCLE05 EQU (0x0<<5)
DCYCLE06 EQU (0x0<<6)
DCYCLE07 EQU (0x0<<7)
DCYCLE08 EQU (0x0<<8)
DCYCLE09 EQU (0x0<<9)
FDCYCLE0 EQU (0x0<<10) ;fdcycle=0 PWM clock (PWM_OUTn) duty cycle is determined by DCYCLE field.fdcycle=1 PWM_OUTn is set high and does not toggle.
PWM_DUTY0_Value EQU (DCYCLE00|DCYCLE01|DCYCLE02|DCYCLE03|DCYCLE04|DCYCLE05|DCYCLE06|DCYCLE07|DCYCLE08|DCYCLE09|FDCYCLE0)
PWM_PERVAL0 EQU 0x40b00008 ;//PWM Period Control Register0
PV00 EQU (0x0<<0)
PV01 EQU (0x0<<1)
PV02 EQU (0x0<<2)
PV03 EQU (0x0<<3)
PV04 EQU (0x0<<4)
PV05 EQU (0x0<<5)
PV06 EQU (0x0<<6)
PV07 EQU (0x0<<7)
PV08 EQU (0x0<<8)
PV09 EQU (0x0<<9)
PWM_PERVAL0_Value EQU (PV00|PV01|PV02|PV03|PV04|PV05|PV06|PV07|PV08|PV09)
PWM_CTRL1 EQU 0x40c00000 ;//PWM Control Registers 1
PRESCALE10 EQU (0x0<<0)
PRESCALE11 EQU (0x0<<1) ;PWMn Prescale Divisor.
PRESCALE12 EQU (0x0<<2) ;Determines the frequency of the PWM module clock (in terms of the 3.86 MHz clock)
PRESCALE13 EQU (0x0<<3) ;PSCLK_PWMn = 3.6864 MHz / (PWM_CTRL[PRESCALE] + 1)
PRESCALE14 EQU (0x0<<4)
PRESCALE15 EQU (0x0<<5)
PWM_SD1 EQU (0x0<<6) ;if pwm_sd=0x0 Graceful shutdown. if pwm_sd=0x1 Abrupt shutdown
PWM_CTRL1_Value EQU (PRESCALE10|PRESCALE11|PRESCALE12|PRESCALE13|PRESCALE14|PRESCALE15|PWM_SD1)
PWM_DUTY1 EQU 0x40c00004 ;//PWM Duty Cycle Registers 1
DCYCLE10 EQU (0x0<<0)
DCYCLE11 EQU (0x0<<1) ;
DCYCLE12 EQU (0x0<<2)
DCYCLE13 EQU (0x0<<3)
DCYCLE14 EQU (0x0<<4)
DCYCLE15 EQU (0x0<<5)
DCYCLE16 EQU (0x0<<6)
DCYCLE17 EQU (0x0<<7)
DCYCLE18 EQU (0x0<<8)
DCYCLE19 EQU (0x0<<9)
FDCYCLE1 EQU (0x0<<10) ;fdcycle=0 PWM clock (PWM_OUTn) duty cycle is determined by DCYCLE field.fdcycle=1 PWM_OUTn is set high and does not toggle.
PWM_DUTY1_Value EQU (DCYCLE10|DCYCLE11|DCYCLE12|DCYCLE13|DCYCLE14|DCYCLE15|DCYCLE16|DCYCLE17|DCYCLE18|DCYCLE19|FDCYCLE1)
PWM_PERVAL1 EQU 0x40c00008 ;//PWM Period Control Register 1
PV10 EQU (0x0<<0)
PV11 EQU (0x0<<1)
PV12 EQU (0x0<<2)
PV13 EQU (0x0<<3)
PV14 EQU (0x0<<4)
PV15 EQU (0x0<<5)
PV16 EQU (0x0<<6)
PV17 EQU (0x0<<7)
PV18 EQU (0x0<<8)
PV19 EQU (0x0<<9)
PWM_PERVAL1_Value EQU (PV10|PV11|PV12|PV13|PV14|PV15|PV16|PV17|PV18|PV19)
END
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