register.s

pxa255,bootloaer ,从初始化中断到GPIO口

PGSR1		EQU		0x40F00024  ;/* Power Manager GPIO Sleep State Register for GP[63-32] */
PGSR2		EQU		0x40F00028  ;/* Power Manager GPIO Sleep State Register for GP[84-64] */
RCSR		EQU		0x40F00030  ;/* Reset Controller Status Register */

;/*  SSP Serial Port Registers */

SSCR0		EQU		0x41000000  ;/* SSP Control Register 0 */
SSCR1		EQU		0x41000004  ;/* SSP Control Register 1 */
SSR			EQU		0x41000008  ;/* SSP Status Register */
SSITR		EQU		0x4100000C  ;/* SSP Interrupt Test Register */
SSDR		EQU		0x41000010  ;/* (Write / Read SSP Data Write Register/SSP Data Read Register */


;/*  MultiMediaCard (MMC controller */

MMC_STRPCL		EQU		0x41100000  ;/* Control to start and stop MMC clock */
MMC_STAT		EQU		0x41100004  ;/* MMC Status Register (read only */
MMC_CLKRT		EQU		0x41100008  ;/* MMC clock rate */
MMC_SPI			EQU		0x4110000c  ;/* SPI mode control bits */
MMC_CMDAT		EQU		0x41100010  ;/* Command/response/data sequence control */
MMC_RESTO		EQU		0x41100014  ;/* Expected response time out */
MMC_RDTO		EQU		0x41100018  ;/* Expected data read time out */
MMC_BLKLEN		EQU		0x4110001c  ;/* Block length of data transaction */
MMC_NOB			EQU		0x41100020  ;/* Number of blocks, for block mode */
MMC_PRTBUF		EQU		0x41100024  ;/* Partial MMC_TXFIFO FIFO written */
MMC_I_MASK		EQU		0x41100028  ;/* Interrupt Mask */
MMC_I_REG		EQU		0x4110002c  ;/* Interrupt Register (read only */
MMC_CMD			EQU		0x41100030  ;/* Index of current command */
MMC_ARGH		EQU		0x41100034  ;/* MSW part of the current command argument */
MMC_ARGL		EQU		0x41100038  ;/* LSW part of the current command argument */
MMC_RES			EQU		0x4110003c  ;/* Response FIFO (read only */
MMC_RXFIFO		EQU		0x41100040  ;/* Receive FIFO (read only */
MMC_TXFIFO		EQU		0x41100044  ;/* Transmit FIFO (write only */

;/* Core Clock */

CCCR			EQU		0x41300000  ;/* Core Clock Configuration Register */
CKEN			EQU		0x41300004  ;/* Clock Enable Register */
OSCC			EQU		0x41300008  ;/* Oscillator Configuration Register */
;CCCR_N_MASK	EQU		0x0380		;/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
;CCCR_M_MASK	EQU		0x0060		;/* Memory Frequency to Run Mode Frequency Multiplier */
;CCCR_L_MASK	EQU		0x001f		;/* Crystal Frequency to Memory Frequency Multiplier */
;CKEN16_LCD	(1 << 16	;/* LCD Unit Clock Enable */
;CKEN14_I2C	(1 << 14	;/* I2C Unit Clock Enable */
;CKEN13_FICP	(1 << 13	;/* FICP Unit Clock Enable */
;CKEN12_MMC	(1 << 12	;/* MMC Unit Clock Enable */
;CKEN11_USB	(1 << 11	;/* USB Unit Clock Enable */
;CKEN8_I2S	(1 << 8	;/* I2S Unit Clock Enable */
;CKEN7_BTUART	(1 << 7	;/* BTUART Unit Clock Enable */
;CKEN6_FFUART	(1 << 6	;/* FFUART Unit Clock Enable */
;CKEN5_STUART	(1 << 5	;/* STUART Unit Clock Enable */
;CKEN3_SSP	(1 << 3	;/* SSP Unit Clock Enable */
;CKEN2_AC97	(1 << 2	;/* AC97 Unit Clock Enable */
;CKEN1_PWM1	(1 << 1	;/* PWM1 Clock Enable */
;CKEN0_PWM0	(1 << 0	;/* PWM0 Clock Enable */
;OSCC_OON	(1 << 1	;/* 32.768kHz OON (write-once only bit */
;SCC_OOK	(1 << 0	;/* 32.768kHz OOK (read-only bit */
      
CCCR_L27    EQU	 0x1	;99.53MHz
CCCR_L32    EQU	 0x2	;117.96MHz	
CCCR_L36    EQU	 0x3	;132.71MHz
CCCR_L40    EQU	 0x4	;147.46MHz
CCCR_L45    EQU	 0x5	;165.89MHz

CCCR_M1     EQU	 0x20	;0x1 << 5  Memory Freq=Crystal Freq * L
CCCR_M2     EQU	 0x40	;0x2 << 5
CCCR_M4     EQU	 0x60	;0x3 << 5

CCCR_N10    EQU	 0x100	;0x2 << 7
CCCR_N15    EQU	 0x180	;0x3 << 7
CCCR_N20    EQU	 0x200	;0x4 << 7
CCCR_N30    EQU	 0x300	;0x6 << 7
;/*   LCD  */

LCCR0		EQU		0x44000000  ;/* LCD Controller Control Register 0 */
LCCR1		EQU		0x44000004  ;/* LCD Controller Control Register 1 */
LCCR2		EQU		0x44000008  ;/* LCD Controller Control Register 2 */
LCCR3		EQU		0x4400000C  ;/* LCD Controller Control Register 3 */
DFBR0		EQU		0x44000020  ;/* DMA Channel 0 Frame Branch Register */
DFBR1		EQU		0x44000024  ;/* DMA Channel 1 Frame Branch Register */
LCSR		EQU		0x44000038  ;/* LCD Controller Status Register */
LIIDR		EQU		0x4400003C  ;/* LCD Controller Interrupt ID Register */
TMEDRGBR	EQU		0x44000040  ;/* TMED RGB Seed Register */
TMEDCR		EQU		0x44000044  ;/* TMED Control Register */
FDADR0		EQU		0x44000200  ;/* DMA Channel 0 Frame Descriptor Address Register */
FSADR0		EQU		0x44000204  ;/* DMA Channel 0 Frame Source Address Register */
FIDR0		EQU		0x44000208  ;/* DMA Channel 0 Frame ID Register */
LDCMD0		EQU		0x4400020C  ;/* DMA Channel 0 Command Register */
FDADR1		EQU		0x44000210  ;/* DMA Channel 1 Frame Descriptor Address Register */
FSADR1		EQU		0x44000214  ;/* DMA Channel 1 Frame Source Address Register */
FIDR1		EQU		0x44000218  ;/* DMA Channel 1 Frame ID Register */
LDCMD1		EQU		0x4400021C  ;/* DMA Channel 1 Command Register */

;/* Memory controller */

MEMC_BASE 			EQU		0x48000000  ;/* Base of Memoriy Controller */
MDCNFG				EQU		0x48000000  ;/* SDRAM Configuration Register 0 */
MDREFR				EQU		0x48000004  ;/* SDRAM Refresh Control Register */
MSC0				EQU		0x48000008  ;/* Static Memory Control Register 0 */
MSC1				EQU		0x4800000C  ;/* Static Memory Control Register 1 */
MSC2				EQU		0x48000010  ;/* Static Memory Control Register 2 */
MECR				EQU		0x48000014  ;/* Expansion Memory (PCMCIA/Compact Flash Bus Configuration */
SXLCR				EQU		0x48000018  ;/* LCR value to be written to SDRAM-Timing Synchronous Flash */
SXCNFG				EQU		0x4800001C  ;/* Synchronous Static Memory Control Register */
SXMRS				EQU		0x48000024  ;/* MRS value to be written to Synchronous Flash or SMROM */
MCMEM0				EQU		0x48000028  ;/* Card interface Common Memory Space Socket 0 Timing */
MCMEM1				EQU		0x4800002C  ;/* Card interface Common Memory Space Socket 1 Timing */
MCATT0				EQU		0x48000030  ;/* Card interface Attribute Space Socket 0 Timing Configuration */
MCATT1				EQU		0x48000034  ;/* Card interface Attribute Space Socket 1 Timing Configuration */
MCIO0				EQU		0x48000038  ;/* Card interface I/O Space Socket 0 Timing Configuration */
MCIO1				EQU		0x4800003C  ;/* Card interface I/O Space Socket 1 Timing Configuration */
MDMRS				EQU		0x48000040  ;/* MRS value to be written to SDRAM */
BOOT_DEF			EQU		0x48000044  ;/* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
MDCNFG_DE0    		EQU		0x00000001
MDCNFG_DE1    		EQU		0x00000002
MDCNFG_DE2     		EQU		0x00010000
MDCNFG_DE3     		EQU		0x00020000
MDCNFG_DWID0   		EQU		0x00000004
MDREFR_E0PIN  		EQU		0x00001000
MDREFR_E1PIN  	 	EQU		0x00008000
MDCNFG_OFFSET  		EQU		0x0
MDREFR_OFFSET  		EQU		0x4
MSC0_OFFSET    		EQU		0x8
MSC1_OFFSET    		EQU		0xC
MSC2_OFFSET    		EQU		0x10
MECR_OFFSET   	 	EQU		0x14
SXLCR_OFFSET   		EQU		0x18
SXCNFG_OFFSET  		EQU		0x1C
FLYCNFG_OFFSET 		EQU		0x20
SXMRS_OFFSET   		EQU		0x24                                       
MCMEM0_OFFSET  		EQU		0x28
MCMEM1_OFFSET  		EQU		0x2C
MCATT0_OFFSET  		EQU		0x30
MCATT1_OFFSET  		EQU		0x34
MCIO0_OFFSET   		EQU		0x38
MCIO1_OFFSET   		EQU		0x3C
MDMRS_OFFSET   		EQU		0x40


;/* General Purpose I/O */

GPLR0		EQU		0x40E00000  ;/* GPIO Pin-Level Register GPIO<31:0> */
GPLR1		EQU		0x40E00004  ;/* GPIO Pin-Level Register GPIO<63:32> */
GPLR2		EQU		0x40E00008  ;/* GPIO Pin-Level Register GPIO<80:64> */

GPDR0		EQU		0x40E0000C  ;/* GPIO Pin Direction Register GPIO<31:0> */
GPDR1		EQU		0x40E00010  ;/* GPIO Pin Direction Register GPIO<63:32> */
GPDR2		EQU		0x40E00014  ;/* GPIO Pin Direction Register GPIO<80:64> */

GPSR0		EQU		0x40E00018  ;/* GPIO Pin Output Set Register GPIO<31:0> */
GPSR1		EQU		0x40E0001C  ;/* GPIO Pin Output Set Register GPIO<63:32> */
GPSR2		EQU		0x40E00020  ;/* GPIO Pin Output Set Register GPIO<80:64> */

GPCR0		EQU		0x40E00024  ;/* GPIO Pin Output Clear Register GPIO<31:0> */
GPCR1		EQU		0x40E00028  ;/* GPIO Pin Output Clear Register GPIO <63:32> */
GPCR2		EQU		0x40E0002C  ;/* GPIO Pin Output Clear Register GPIO <80:64> */

GRER0		EQU		0x40E00030  ;/* GPIO Rising-Edge Detect Register GPIO<31:0> */
GRER1		EQU		0x40E00034  ;/* GPIO Rising-Edge Detect Register GPIO<63:32> */
GRER2		EQU		0x40E00038  ;/* GPIO Rising-Edge Detect Register GPIO<80:64> */

GFER0		EQU		0x40E0003C  ;/* GPIO Falling-Edge Detect Register GPIO<31:0> */
GFER1		EQU		0x40E00040  ;/* GPIO Falling-Edge Detect Register GPIO<63:32> */
GFER2		EQU		0x40E00044  ;/* GPIO Falling-Edge Detect Register GPIO<80:64> */
GEDR0		EQU		0x40E00048  ;/* GPIO Edge Detect Status Register GPIO<31:0> */
EDR1		EQU		0x40E0004C  ;/* GPIO Edge Detect Status Register GPIO<63:32> */
GEDR2		EQU		0x40E00050  ;/* GPIO Edge Detect Status Register GPIO<80:64> */
GAFR0_L		EQU		0x40E00054  ;/* GPIO Alternate Function Select Register GPIO<15:0> */
GAFR0_U		EQU		0x40E00058  ;/* GPIO Alternate Function Select Register GPIO<31:16> */
GAFR1_L		EQU		0x40E0005C  ;/* GPIO Alternate Function Select Register GPIO<47:32> */
GAFR1_U		EQU		0x40E00060  ;/* GPIO Alternate Function Select Register GPIO<63:48> */
GAFR2_L		EQU		0x40E00064  ;/* GPIO Alternate Function Select Register GPIO<79:64> */
GAFR2_U		EQU		0x40E00068  ;/* GPIO Alternate Function Select Register GPIO 80 */



;/* GPIO alternate function assignments */

;GPIO1_RST			1	;/* reset */
;GPIO6_MMCCLK		6	;/* MMC Clock */
;GPIO8_48MHz		7	;/* 48 MHz clock output */
;GPIO8_MMCCS0		8	;/* MMC Chip Select 0 */
;GPIO9_MMCCS1		9	;/* MMC Chip Select 1 */
;GPIO10_RTCCLK		10	;/* real time clock (1 Hz */
;GPIO11_3_6MHz		11	;/* 3.6 MHz oscillator out */
;GPIO12_32KHz		12	;/* 32 kHz out */
;GPIO13_MBGNT		13	;/* memory controller grant */
;GPIO14_MBREQ		14	;/* alternate bus master request */
;GPIO15_nCS_1		15	;/* chip select 1 */
;GPIO16_PWM0		16	;/* PWM0 output */
;GPIO17_PWM1		17	;/* PWM1 output */
;GPIO18_RDY			18	;/* Ext. Bus Ready */
;GPIO19_DREQ1		19	;/* External DMA Request */
;GPIO20_DREQ0		20	;/* External DMA Request */
;GPIO23_SCLK		23	;/* SSP clock */
;GPIO24_SFRM		24	;/* SSP Frame */
;GPIO25_STXD		25	;/* SSP transmit */
;GPIO26_SRXD		26	;/* SSP receive */
;GPIO27_SEXTCLK		27	;/* SSP ext_clk */
;GPIO28_BITCLK		28	;/* AC97/I2S bit_clk */
;GPIO29_SDATA_IN	29	;/* AC97 Sdata_in0 / I2S Sdata_in */
;GPIO30_SDATA_OUT	30	;/* AC97/I2S Sdata_out */
;GPIO31_SYNC		31	;/* AC97/I2S sync */
;GPIO32_SDATA_IN1	32	;/* AC97 Sdata_in1 */
;GPIO33_nCS_5		33	;/* chip select 5 */
;GPIO34_FFRXD		34	;/* FFUART receive */
;GPIO34_MMCCS0		34	;/* MMC Chip Select 0 */
;GPIO35_FFCTS		35	;/* FFUART Clear to send */
;GPIO36_FFDCD		36	;/* FFUART Data carrier detect */
;GPIO37_FFDSR		37	;/* FFUART data set ready */
;GPIO38_FFRI		38	;/* FFUART Ring Indicator */
;GPIO39_MMCCS1		39	;/* MMC Chip Select 1 */
;GPIO39_FFTXD		39	;/* FFUART transmit data */
;GPIO40_FFDTR		40	;/* FFUART data terminal Ready */
;GPIO41_FFRTS		41	;/* FFUART request to send */
;GPIO42_BTRXD		42	;/* BTUART receive data */
;GPIO43_BTTXD		43	;/* BTUART transmit data */
;GPIO44_BTCTS		44	;/* BTUART clear to send */
;GPIO45_BTRTS		45	;/* BTUART request to send */
;GPIO46_ICPRXD		46	;/* ICP receive data */
;GPIO46_STRXD		46	;/* STD_UART receive data */
;GPIO47_ICPTXD		47	;/* ICP transmit data */
;GPIO47_STTXD		47	;/* STD_UART transmit data */
;GPIO48_nPOE		48	;/* Output Enable for Card Space */
;GPIO49_nPWE		49	;/* Write Enable for Card Space */
;GPIO50_nPIOR		50	;/* I/O Read for Card Space */
;GPIO51_nPIOW		51	;/* I/O Write for Card Space */
;GPIO52_nPCE_1		52	;/* Card Enable for Card Space */
;GPIO53_nPCE_2		53	;/* Card Enable for Card Space */
;GPIO53_MMCCLK		53	;/* MMC Clock */
;GPIO54_MMCCLK		54	;/* MMC Clock */
;GPIO54_pSKTSEL		54	;/* Socket Select for Card Space */
;GPIO55_nPREG		55	;/* Card Address bit 26 */;
;GPIO56_nPWAIT		56	;/* Wait signal for Card Space */
;GPIO57_nIOIS16		57	;/* Bus Width select for I/O Card Space */
;GPIO58_LDD_0		58	;/* LCD data pin 0 */
;GPIO59_LDD_1		59	;/* LCD data pin 1 */
;GPIO60_LDD_2		60	;/* LCD data pin 2 */
;GPIO61_LDD_3		61	;/* LCD data pin 3 */
;GPIO62_LDD_4		62	;/* LCD data pin 4 */
;GPIO63_LDD_5		63	;/* LCD data pin 5 */
;GPIO64_LDD_6		64	;/* LCD data pin 6 */
;GPIO65_LDD_7		65	;/* LCD data pin 7 */
;GPIO66_LDD_8		66	;/* LCD data pin 8 */
;GPIO66_MBREQ		66	;/* alternate bus master req */
;GPIO67_LDD_9		67	;/* LCD data pin 9 */
;GPIO67_MMCCS0		67	;/* MMC Chip Select 0 */
;GPIO68_LDD_10		68	;/* LCD data pin 10 */
;GPIO68_MMCCS1		68	;/* MMC Chip Select 1 */
;GPIO69_LDD_11		69	;/* LCD data pin 11 */
;GPIO69_MMCCLK		69	;/* MMC_CLK */
;GPIO70_LDD_12		70	;/* LCD data pin 12 */
;GPIO70_RTCCLK		70	;/* Real Time clock (1 Hz */
;GPIO71_LDD_13		71	;/* LCD data pin 13 */
;GPIO71_3_6MHz		71	;/* 3.6 MHz Oscillator clock */
;GPIO72_LDD_14		72	;/* LCD data pin 14 */
;GPIO72_32kHz		72	;/* 32 kHz clock */
;GPIO73_LDD_15		73	;/* LCD data pin 15 */
;GPIO73_MBGNT		73	;/* Memory controller grant */
;GPIO74_LCD_FCLK	74	;/* LCD Frame clock */
;GPIO75_LCD_LCLK	75	;/* LCD line clock */
;GPIO76_LCD_PCLK	76	;/* LCD Pixel clock */
;GPIO77_LCD_ACBIAS	77	;/* LCD AC Bias */
;GPIO78_nCS_2		78	;/* chip select 2 */
;GPIO79_nCS_3		79	;/* chip select 3 */
;GPIO80_nCS_4		80	;/* chip select 4 */



;/*************************************************************
;****************Interrupt Controller Register*****************
;*************************************************************/
ICIP		EQU		0x40d00000		;//Interrupt Controller IRQ Pending Register
IP8			EQU		(0x0<<8)			;;if IP[x]=0x0,IRQ NOT requested by any enabled source.
IP9			EQU		(0x0<<9)			;;if IP[x]=0x1,IRQ requested by an enabled source.
IP10		EQU		(0x0<<10)
IP11		EQU		(0x0<<11)
IP12		EQU		(0x0<<12)
IP13		EQU		(0x0<<13)
IP14		EQU		(0x0<<14)			
IP17		EQU		(0x0<<17)
IP18		EQU		(0x0<<18)
IP19		EQU		(0x0<<19)
IP20		EQU		(0x0<<20)
IP21		EQU		(0x0<<21)
IP22		EQU		(0x0<<22)
IP23		EQU		(0x0<<23)
IP24		EQU		(0x0<<24)
IP25		EQU		(0x0<<25)
IP26		EQU		(0x0<<26)
IP27		EQU		(0x0<<27)
IP28		EQU		(0x0<<28)
IP29		EQU		(0x0<<29)
IP30		EQU		(0x0<<30)
IP31		EQU		(0x0<<31)
ICIP_Value	EQU		(IP8|IP9|IP10|IP11|IP12|IP13|IP14|IP17|IP18|IP19|IP20|IP21|IP22|IP23|IP24|IP25|IP26|IP27|IP28|IP29|IP30|IP31)

ICMR 		EQU		0x40d00004 		;//Interrupt Controller Mask Register