📄 register.s
字号:
;/* PXA Chip selects*/
; PXA_CS0_PHYS EQU 0x00000000
; PXA_CS1_PHYS EQU 0x04000000
; PXA_CS2_PHYS EQU 0x08000000
; PXA_CS3_PHYS EQU 0x0C000000
; PXA_CS4_PHYS EQU 0x10000000
; PXA_CS5_PHYS EQU 0x14000000
; PXA_SDRAMCS0 EQU 0xA0000000
; PXA_SDRAMCS1 EQU 0xA4000000
; PXA_SDRAMCS2 EQU 0xA8000000
; PXA_SDRAMCS3 EQU 0xAC000000
;/* DMA Controller*/
DCSR0 EQU 0x40000000 ;/* DMA Control / Status Register for Channel 0 */
DCSR1 EQU 0x40000004 ;/* DMA Control / Status Register for Channel 1 */
DCSR2 EQU 0x40000008 ;/* DMA Control / Status Register for Channel 2 */
DCSR3 EQU 0x4000000c ;/* DMA Control / Status Register for Channel 3 */
DCSR4 EQU 0x40000010 ;/* DMA Control / Status Register for Channel 4 */
DCSR5 EQU 0x40000014 ;/* DMA Control / Status Register for Channel 5 */
DCSR6 EQU 0x40000018 ;/* DMA Control / Status Register for Channel 6 */
DCSR7 EQU 0x4000001c ;/* DMA Control / Status Register for Channel 7 */
DCSR8 EQU 0x40000020 ;/* DMA Control / Status Register for Channel 8 */
DCSR9 EQU 0x40000024 ;/* DMA Control / Status Register for Channel 9 */
DCSR10 EQU 0x40000028 ;/* DMA Control / Status Register for Channel 10 */
DCSR11 EQU 0x4000002c ;/* DMA Control / Status Register for Channel 11 */
DCSR12 EQU 0x40000030 ;/* DMA Control / Status Register for Channel 12 */
DCSR13 EQU 0x40000034 ;/* DMA Control / Status Register for Channel 13 */
DCSR14 EQU 0x40000038 ;/* DMA Control / Status Register for Channel 14 */
DCSR15 EQU 0x4000003c ;/* DMA Control / Status Register for Channel 15 */
DINT EQU 0x400000f0 ;/* DMA Interrupt Register */
DRCMR0 EQU 0x40000100 ;/* Request to Channel Map Register for DREQ 0 */
DRCMR1 EQU 0x40000104 ;/* Request to Channel Map Register for DREQ 1 */
DRCMR2 EQU 0x40000108 ;/* Request to Channel Map Register for I2S receive Request */
DRCMR3 EQU 0x4000010c ;/* Request to Channel Map Register for I2S transmit Request */
DRCMR4 EQU 0x40000110 ;/* Request to Channel Map Register for BTUART receive Request */
DRCMR5 EQU 0x40000114 ;/* Request to Channel Map Register for BTUART transmit Request. */
DRCMR6 EQU 0x40000118 ;/* Request to Channel Map Register for FFUART receive Request */
DRCMR7 EQU 0x4000011c ;/* Request to Channel Map Register for FFUART transmit Request */
DRCMR8 EQU 0x40000120 ;/* Request to Channel Map Register for AC97 microphone Request */
DRCMR9 EQU 0x40000124 ;/* Request to Channel Map Register for AC97 modem receive Request */
DRCMR10 EQU 0x40000128 ;/* Request to Channel Map Register for AC97 modem transmit Request */
DRCMR11 EQU 0x4000012c ;/* Request to Channel Map Register for AC97 audio receive Request */
DRCMR12 EQU 0x40000130 ;/* Request to Channel Map Register for AC97 audio transmit Request */
DRCMR13 EQU 0x40000134 ;/* Request to Channel Map Register for SSP receive Request */
DRCMR14 EQU 0x40000138 ;/* Request to Channel Map Register for SSP transmit Request */
DRCMR15 EQU 0x4000013c ;/* Reserved */
DRCMR16 EQU 0x40000140 ;/* Reserved */
DRCMR17 EQU 0x40000144 ;/* Request to Channel Map Register for ICP receive Request */
DRCMR18 EQU 0x40000148 ;/* Request to Channel Map Register for ICP transmit Request */
DRCMR19 EQU 0x4000014c ;/* Request to Channel Map Register for STUART receive Request */
DRCMR20 EQU 0x40000150 ;/* Request to Channel Map Register for STUART transmit Request */
DRCMR21 EQU 0x40000154 ;/* Request to Channel Map Register for MMC receive Request */
DRCMR22 EQU 0x40000158 ;/* Request to Channel Map Register for MMC transmit Request */
DRCMR23 EQU 0x4000015c ;/* Reserved */
DRCMR24 EQU 0x40000160 ;/* Reserved */
DRCMR25 EQU 0x40000164 ;/* Request to Channel Map Register for USB endpoint 1 Request */
DRCMR26 EQU 0x40000168 ;/* Request to Channel Map Register for USB endpoint 2 Request */
DRCMR27 EQU 0x4000016C ;/* Request to Channel Map Register for USB endpoint 3 Request */
DRCMR28 EQU 0x40000170 ;/* Request to Channel Map Register for USB endpoint 4 Request */
DRCMR29 EQU 0x40000174 ;/* Reserved */
DRCMR30 EQU 0x40000178 ;/* Request to Channel Map Register for USB endpoint 6 Request */
DRCMR31 EQU 0x4000017C ;/* Request to Channel Map Register for USB endpoint 7 Request */
DRCMR32 EQU 0x40000180 ;/* Request to Channel Map Register for USB endpoint 8 Request */
DRCMR33 EQU 0x40000184 ;/* Request to Channel Map Register for USB endpoint 9 Request */
DRCMR34 EQU 0x40000188 ;/* Reserved */
DRCMR35 EQU 0x4000018C ;/* Request to Channel Map Register for USB endpoint 11 Request */
DRCMR36 EQU 0x40000190 ;/* Request to Channel Map Register for USB endpoint 12 Request */
DRCMR37 EQU 0x40000194 ;/* Request to Channel Map Register for USB endpoint 13 Request */
DRCMR38 EQU 0x40000198 ;/* Request to Channel Map Register for USB endpoint 14 Request */
DRCMR39 EQU 0x4000019C ;/* Reserved */
DDADR0 EQU 0x40000200 ;/* DMA Descriptor Address Register Channel 0 */
DSADR0 EQU 0x40000204 ;/* DMA Source Address Register Channel 0 */
DTADR0 EQU 0x40000208 ;/* DMA Target Address Register Channel 0 */
DCMD0 EQU 0x4000020c ;/* DMA Command Address Register Channel 0 */
DDADR1 EQU 0x40000210 ;/* DMA Descriptor Address Register Channel 1 */
DSADR1 EQU 0x40000214 ;/* DMA Source Address Register Channel 1 */
DTADR1 EQU 0x40000218 ;/* DMA Target Address Register Channel 1 */
DCMD1 EQU 0x4000021c ;/* DMA Command Address Register Channel 1 */
DDADR2 EQU 0x40000220 ;/* DMA Descriptor Address Register Channel 2 */
DSADR2 EQU 0x40000224 ;/* DMA Source Address Register Channel 2 */
DTADR2 EQU 0x40000228 ;/* DMA Target Address Register Channel 2 */
DCMD2 EQU 0x4000022c ;/* DMA Command Address Register Channel 2 */
DDADR3 EQU 0x40000230 ;/* DMA Descriptor Address Register Channel 3 */
DSADR3 EQU 0x40000234 ;/* DMA Source Address Register Channel 3 */
DTADR3 EQU 0x40000238 ;/* DMA Target Address Register Channel 3 */
DCMD3 EQU 0x4000023c ;/* DMA Command Address Register Channel 3 */
DDADR4 EQU 0x40000240 ;/* DMA Descriptor Address Register Channel 4 */
DSADR4 EQU 0x40000244 ;/* DMA Source Address Register Channel 4 */
DTADR4 EQU 0x40000248 ;/* DMA Target Address Register Channel 4 */
DCMD4 EQU 0x4000024c ;/* DMA Command Address Register Channel 4 */
DDADR5 EQU 0x40000250 ;/* DMA Descriptor Address Register Channel 5 */
DSADR5 EQU 0x40000254 ;/* DMA Source Address Register Channel 5 */
DTADR5 EQU 0x40000258 ;/* DMA Target Address Register Channel 5 */
DCMD5 EQU 0x4000025c ;/* DMA Command Address Register Channel 5 */
DDADR6 EQU 0x40000260 ;/* DMA Descriptor Address Register Channel 6 */
DSADR6 EQU 0x40000264 ;/* DMA Source Address Register Channel 6 */
DTADR6 EQU 0x40000268 ;/* DMA Target Address Register Channel 6 */
DCMD6 EQU 0x4000026c ;/* DMA Command Address Register Channel 6 */
DDADR7 EQU 0x40000270 ;/* DMA Descriptor Address Register Channel 7 */
DSADR7 EQU 0x40000274 ;/* DMA Source Address Register Channel 7 */
DTADR7 EQU 0x40000278 ;/* DMA Target Address Register Channel 7 */
DCMD7 EQU 0x4000027c ;/* DMA Command Address Register Channel 7 */
DDADR8 EQU 0x40000280 ;/* DMA Descriptor Address Register Channel 8 */
DSADR8 EQU 0x40000284 ;/* DMA Source Address Register Channel 8 */
DTADR8 EQU 0x40000288 ;/* DMA Target Address Register Channel 8 */
DCMD8 EQU 0x4000028c ;/* DMA Command Address Register Channel 8 */
DDADR9 EQU 0x40000290 ;/* DMA Descriptor Address Register Channel 9 */
DSADR9 EQU 0x40000294 ;/* DMA Source Address Register Channel 9 */
DTADR9 EQU 0x40000298 ;/* DMA Target Address Register Channel 9 */
DCMD9 EQU 0x4000029c ;/* DMA Command Address Register Channel 9 */
DDADR10 EQU 0x400002a0 ;/* DMA Descriptor Address Register Channel 10 */
DSADR10 EQU 0x400002a4 ;/* DMA Source Address Register Channel 10 */
DTADR10 EQU 0x400002a8 ;/* DMA Target Address Register Channel 10 */
DCMD10 EQU 0x400002ac ;/* DMA Command Address Register Channel 10 */
DDADR11 EQU 0x400002b0 ;/* DMA Descriptor Address Register Channel 11 */
DSADR11 EQU 0x400002b4 ;/* DMA Source Address Register Channel 11 */
DTADR11 EQU 0x400002b8 ;/* DMA Target Address Register Channel 11 */
DCMD11 EQU 0x400002bc ;/* DMA Command Address Register Channel 11 */
DDADR12 EQU 0x400002c0 ;/* DMA Descriptor Address Register Channel 12 */
DSADR12 EQU 0x400002c4 ;/* DMA Source Address Register Channel 12 */
DTADR12 EQU 0x400002c8 ;/* DMA Target Address Register Channel 12 */
DCMD12 EQU 0x400002cc ;/* DMA Command Address Register Channel 12 */
DDADR13 EQU 0x400002d0 ;/* DMA Descriptor Address Register Channel 13 */
DSADR13 EQU 0x400002d4 ;/* DMA Source Address Register Channel 13 */
DTADR13 EQU 0x400002d8 ;/* DMA Target Address Register Channel 13 */
DCMD13 EQU 0x400002dc ;/* DMA Command Address Register Channel 13 */
DDADR14 EQU 0x400002e0 ;/* DMA Descriptor Address Register Channel 14 */
DSADR14 EQU 0x400002e4 ;/* DMA Source Address Register Channel 14 */
DTADR14 EQU 0x400002e8 ;/* DMA Target Address Register Channel 14 */
DCMD14 EQU 0x400002ec ;/* DMA Command Address Register Channel 14 */
DDADR15 EQU 0x400002f0 ;/* DMA Descriptor Address Register Channel 15 */
DSADR15 EQU 0x400002f4 ;/* DMA Source Address Register Channel 15 */
DTADR15 EQU 0x400002f8 ;/* DMA Target Address Register Channel 15 */
DCMD15 EQU 0x400002fc ;/* DMA Command Address Register Channel 15 */
;/* Full Function UART (FFUART */
;FFUART FFRBR
FFRBR EQU 0x40100000 ;/* Receive Buffer Register (read only */
FFTHR EQU 0x40100000 ;/* Transmit Holding Register (write only */
FFIER EQU 0x40100004 ;/* Interrupt Enable Register (read/write */
FFIIR EQU 0x40100008 ;/* Interrupt ID Register (read only */
FFFCR EQU 0x40100008 ;/* FIFO Control Register (write only */
FFLCR EQU 0x4010000C ;/* Line Control Register (read/write */
FFMCR EQU 0x40100010 ;/* Modem Control Register (read/write */
FFLSR EQU 0x40100014 ;/* Line Status Register (read only */
FFMSR EQU 0x40100018 ;/* Modem Status Register (read only */
FFSPR EQU 0x4010001C ;/* Scratch Pad Register (read/write */
FFISR EQU 0x40100020 ;/* Infrared Selection Register (read/write */
FFDLL EQU 0x40100000 ;/* Divisor Latch Low Register (DLAB = 1 (read/write */
FFDLH EQU 0x40100004 ;/* Divisor Latch High Register (DLAB = 1 (read/write */
;/* Bluetooth UART (BTUART */
;BTUART BTRBR
BTRBR EQU 0x40200000 ;/* Receive Buffer Register (read only */
BTTHR EQU 0x40200000 ;/* Transmit Holding Register (write only */
BTIER EQU 0x40200004 ;/* Interrupt Enable Register (read/write */
BTIIR EQU 0x40200008 ;/* Interrupt ID Register (read only */
BTFCR EQU 0x40200008 ;/* FIFO Control Register (write only */
BTLCR EQU 0x4020000C ;/* Line Control Register (read/write */
BTMCR EQU 0x40200010 ;/* Modem Control Register (read/write */
BTLSR EQU 0x40200014 ;/* Line Status Register (read only */
BTMSR EQU 0x40200018 ;/* Modem Status Register (read only */
BTSPR EQU 0x4020001C ;/* Scratch Pad Register (read/write */
BTISR EQU 0x40200020 ;/* Infrared Selection Register (read/write */
BTDLL EQU 0x40200000 ;/* Divisor Latch Low Register (DLAB = 1 (read/write */
BTDLH EQU 0x40200004 ;/* Divisor Latch High Register (DLAB = 1 (read/write */
;/* Standard UART (STUART */
;STUART STRBR
STRBR EQU 0x40700000 ;/* Receive Buffer Register (read only */
STTHR EQU 0x40700000 ;/* Transmit Holding Register (write only */
STIER EQU 0x40700004 ;/* Interrupt Enable Register (read/write */
STIIR EQU 0x40700008 ;/* Interrupt ID Register (read only */
STFCR EQU 0x40700008 ;/* FIFO Control Register (write only */
STLCR EQU 0x4070000C ;/* Line Control Register (read/write */
STMCR EQU 0x40700010 ;/* Modem Control Register (read/write */
STLSR EQU 0x40700014 ;/* Line Status Register (read only */
STMSR EQU 0x40700018 ;/* Reserved */
STSPR EQU 0x4070001C ;/* Scratch Pad Register (read/write */
STISR EQU 0x40700020 ;/* Infrared Selection Register (read/write */
STDLL EQU 0x40700000 ;/* Divisor Latch Low Register (DLAB = 1 (read/write */
STDLH EQU 0x40700004 ;/* Divisor Latch High Register (DLAB = 1 (read/write */
;/* I2C registers */
IBMR EQU 0x40301680 ;/* I2C Bus Monitor Register - IBMR */
IDBR EQU 0x40301688 ;/* I2C Data Buffer Register - IDBR */
ICR EQU 0x40301690 ;/* I2C Control Register - ICR */
ISR EQU 0x40301698 ;/* I2C Status Register - ISR */
ISAR EQU 0x403016A0 ;/* I2C Slave Address Register - ISAR */
;/* Serial Audio Controller */
;/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
;* short defines because there is too much chance of namespace collision */
;// SACR0 EQU 0x40400000 ;/* Global Control Register */
;/ SACR1 EQU 0x40400004 ;/* Serial Audio I 2 S/MSB-Justified Control Register */
;// SASR0 EQU 0x4040000C ;/* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
;// SAIMR EQU 0x40400014 ;/* Serial Audio Interrupt Mask Register */
;// SAICR EQU 0x40400018 ;/* Serial Audio Interrupt Clear Register */
;// SADIV EQU 0x40400060 ;/* Audio Clock Divider Register. */
;// SADR EQU 0x40400080 ;/* Serial Audio Data Register (TX and RX FIFO access Register. */
;/* AC97 Controller registers */
POCR EQU 0x40500000 ;/* PCM Out Control Register */
PICR EQU 0x40500004 ;/* PCM In Control Register */
MCCR EQU 0x40500008 ;/* Mic In Control Register */
GCR EQU 0x4050000C ;/* Global Control Register */
POSR EQU 0x40500010 ;/* PCM Out Status Register */
PISR EQU 0x40500014 ;/* PCM In Status Register */
MCSR EQU 0x40500018 ;/* Mic In Status Register */
GSR EQU 0x4050001C ;/* Global Status Register */
CAR EQU 0x40500020 ;/* CODEC Access Register */
PCDR EQU 0x40500040 ;/* PCM FIFO Data Register */
MCDR EQU 0x40500060 ;/* Mic-in FIFO Data Register */
MOCR EQU 0x40500100 ;/* Modem Out Control Register */
MICR EQU 0x40500108 ;/* Modem In Control Register */
MOSR EQU 0x40500110 ;/* Modem Out Status Register */
MISR EQU 0x40500118 ;/* Modem In Status Register */
MODR EQU 0x40500140 ;/* Modem FIFO Data Register */
PAC_REG_BASE EQU 0x40500200 ;/* Primary Audio Codec */
SAC_REG_BASE EQU 0x40500300 ;/* Secondary Audio Codec */
PMC_REG_BASE EQU 0x40500400 ;/* Primary Modem Codec */
SMC_REG_BASE EQU 0x40500500 ;/* Secondary Modem Codec */
;/* USB Device Controller */
UDCCR EQU 0x40600000 ;/* UDC Control Register */
UDCCS0 EQU 0x40600010 ;/* UDC Endpoint 0 Control/Status Register */
UDCCS1 EQU 0x40600014 ;/* UDC Endpoint 1 (IN Control/Status Register */
UDCCS2 EQU 0x40600018 ;/* UDC Endpoint 2 (OUT Control/Status Register */
UDCCS3 EQU 0x4060001C ;/* UDC Endpoint 3 (IN Control/Status Register */
UDCCS4 EQU 0x40600020 ;/* UDC Endpoint 4 (OUT Control/Status Register */
UDCCS5 EQU 0x40600024 ;/* UDC Endpoint 5 (Interrupt Control/Status Register */
UDCCS6 EQU 0x40600028 ;/* UDC Endpoint 6 (IN Control/Status Register */
UDCCS7 EQU 0x4060002C ;/* UDC Endpoint 7 (OUT Control/Status Register */
UDCCS8 EQU 0x40600030 ;/* UDC Endpoint 8 (IN Control/Status Register */
UDCCS9 EQU 0x40600034 ;/* UDC Endpoint 9 (OUT Control/Status Register */
UDCCS10 EQU 0x40600038 ;/* UDC Endpoint 10 (Interrupt Control/Status Register */
UDCCS11 EQU 0x4060003C ;/* UDC Endpoint 11 (IN Control/Status Register */
UDCCS12 EQU 0x40600040 ;/* UDC Endpoint 12 (OUT Control/Status Register */
UDCCS13 EQU 0x40600044 ;/* UDC Endpoint 13 (IN Control/Status Register */
UDCCS14 EQU 0x40600048 ;/* UDC Endpoint 14 (OUT Control/Status Register */
UDCCS15 EQU 0x4060004C ;/* UDC Endpoint 15 (Interrupt Control/Status Register */
UFNRH EQU 0x40600060 ;/* UDC Frame Number Register High */
UFNRL EQU 0x40600064 ;/* UDC Frame Number Register Low */
UBCR2 EQU 0x40600068 ;/* UDC Byte Count Reg 2 */
UBCR4 EQU 0x4060006c ;/* UDC Byte Count Reg 4 */
UBCR7 EQU 0x40600070 ;/* UDC Byte Count Reg 7 */
UBCR9 EQU 0x40600074 ;/* UDC Byte Count Reg 9 */
UBCR12 EQU 0x40600078 ;/* UDC Byte Count Reg 12 */
UBCR14 EQU 0x4060007c ;/* UDC Byte Count Reg 14 */
UDDR0 EQU 0x40600080 ;/* UDC Endpoint 0 Data Register */
UDDR1 EQU 0x40600100 ;/* UDC Endpoint 1 Data Register */
UDDR2 EQU 0x40600180 ;/* UDC Endpoint 2 Data Register */
UDDR3 EQU 0x40600200 ;/* UDC Endpoint 3 Data Register */
UDDR4 EQU 0x40600400 ;/* UDC Endpoint 4 Data Register */
UDDR5 EQU 0x406000A0 ;/* UDC Endpoint 5 Data Register */
UDDR6 EQU 0x40600600 ;/* UDC Endpoint 6 Data Register */
UDDR7 EQU 0x40600680 ;/* UDC Endpoint 7 Data Register */
UDDR8 EQU 0x40600700 ;/* UDC Endpoint 8 Data Register */
UDDR9 EQU 0x40600900 ;/* UDC Endpoint 9 Data Register */
UDDR10 EQU 0x406000C0 ;/* UDC Endpoint 10 Data Register */
UDDR11 EQU 0x40600B00 ;/* UDC Endpoint 11 Data Register */
UDDR12 EQU 0x40600B80 ;/* UDC Endpoint 12 Data Register */
UDDR13 EQU 0x40600C00 ;/* UDC Endpoint 13 Data Register */
UDDR14 EQU 0x40600E00 ;/* UDC Endpoint 14 Data Register */
UDDR15 EQU 0x406000E0 ;/* UDC Endpoint 15 Data Register */
UICR0 EQU 0x40600050 ;/* UDC Interrupt Control Register 0 */
UICR1 EQU 0x40600054 ;/* UDC Interrupt Control Register 1 */
USIR0 EQU 0x40600058 ;/* UDC Status Interrupt Register 0 */
USIR1 EQU 0x4060005C ;/* UDC Status Interrupt Register 1 */
;/* Fast Infrared Communication Port */
ICCR0 EQU 0x40800000 ;/* ICP Control Register 0 */
ICCR1 EQU 0x40800004 ;/* ICP Control Register 1 */
ICCR2 EQU 0x40800008 ;/* ICP Control Register 2 */
ICDR EQU 0x4080000c ;/* ICP Data Register */
ICSR0 EQU 0x40800014 ;/* ICP Status Register 0 */
ICSR1 EQU 0x40800018 ;/* ICP Status Register 1 */
;/* Power Manager */
PMCR EQU 0x40F00000 ;/* Power Manager Control Register */
PSSR EQU 0x40F00004 ;/* Power Manager Sleep Status Register */
PSPR EQU 0x40F00008 ;/* Power Manager Scratch Pad Register */
PWER EQU 0x40F0000C ;/* Power Manager Wake-up Enable Register */
PRER EQU 0x40F00010 ;/* Power Manager GPIO Rising-Edge Detect Enable Register */
PFER EQU 0x40F00014 ;/* Power Manager GPIO Falling-Edge Detect Enable Register */
PEDR EQU 0x40F00018 ;/* Power Manager GPIO Edge Detect Status Register */
PCFR EQU 0x40F0001C ;/* Power Manager General Configuration Register */
PGSR0 EQU 0x40F00020 ;/* Power Manager GPIO Sleep State Register for GP[31-0] */
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