📄 gpio_config.s
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PC45 EQU (0x0<<13)
PC46 EQU (0x0<<14)
PC47 EQU (0x0<<15)
PC48 EQU (0x0<<16)
PC49 EQU (0x0<<17)
PC50 EQU (0x0<<18)
PC51 EQU (0x0<<19)
PC52 EQU (0x0<<20)
PC53 EQU (0x0<<21)
PC54 EQU (0x0<<22)
PC55 EQU (0x0<<23)
PC56 EQU (0x0<<24)
PC57 EQU (0x0<<25)
PC58 EQU (0x0<<26)
PC59 EQU (0x0<<27)
PC60 EQU (0x0<<28)
PC61 EQU (0x0<<29)
PC62 EQU (0x0<<30)
PC63 EQU (0x0<<31)
;// GPCR2 0x40e0002c if PC[x]=0,No affect.if PC[x]=1,output 0
PC64 EQU (0x0<<0)
PC65 EQU (0x0<<1)
PC66 EQU (0x0<<2)
PC67 EQU (0x0<<3)
PC68 EQU (0x0<<4)
PC69 EQU (0x0<<5)
PC70 EQU (0x0<<6)
PC71 EQU (0x0<<7)
PC72 EQU (0x0<<8)
PC73 EQU (0x0<<9)
PC74 EQU (0x0<<10)
PC75 EQU (0x0<<11)
PC76 EQU (0x0<<12)
PC77 EQU (0x0<<13)
PC78 EQU (0x0<<14)
PC79 EQU (0x0<<15)
PC80 EQU (0x0<<16)
PC81 EQU (0x0<<17)
PC82 EQU (0x0<<18)
PC83 EQU (0x0<<19)
PC84 EQU (0x0<<20)
;// GRER0 0x40e00030 if RE[x]=0,Disable rising-edge detect enable.
;// if RE[x]=1,Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
RE0 EQU (0x0<<0)
RE1 EQU (0x0<<1)
RE2 EQU (0x0<<2)
RE3 EQU (0x0<<3)
RE4 EQU (0x0<<4)
RE5 EQU (0x0<<5)
RE6 EQU (0x0<<6)
RE7 EQU (0x0<<7)
RE8 EQU (0x0<<8)
RE9 EQU (0x0<<9)
RE10 EQU (0x0<<10)
RE11 EQU (0x0<<11)
RE12 EQU (0x0<<12)
RE13 EQU (0x0<<13)
RE14 EQU (0x0<<14)
RE15 EQU (0x0<<15)
RE16 EQU (0x0<<16)
RE17 EQU (0x0<<17)
RE18 EQU (0x0<<18)
RE19 EQU (0x0<<19)
RE20 EQU (0x0<<20)
RE21 EQU (0x0<<21)
RE22 EQU (0x0<<22)
RE23 EQU (0x0<<23)
RE24 EQU (0x0<<24)
RE25 EQU (0x0<<25)
RE26 EQU (0x0<<26)
RE27 EQU (0x0<<27)
RE28 EQU (0x0<<28)
RE29 EQU (0x0<<29)
RE30 EQU (0x0<<30)
RE31 EQU (0x0<<31)
;// GRER1 0x40e00034 if RE[x]=0,Disable rising-edge detect enable.
;//if RE[x]=1,Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
RE32 EQU (0x0<<0)
RE33 EQU (0x0<<1)
RE34 EQU (0x0<<2)
RE35 EQU (0x0<<3)
RE36 EQU (0x0<<4)
RE37 EQU (0x0<<5)
RE38 EQU (0x0<<6)
RE39 EQU (0x0<<7)
RE40 EQU (0x0<<8)
RE41 EQU (0x0<<9)
RE42 EQU (0x0<<10)
RE43 EQU (0x0<<11)
RE44 EQU (0x0<<12)
RE45 EQU (0x0<<13)
RE46 EQU (0x0<<14)
RE47 EQU (0x0<<15)
RE48 EQU (0x0<<16)
RE49 EQU (0x0<<17)
RE50 EQU (0x0<<18)
RE51 EQU (0x0<<19)
RE52 EQU (0x0<<20)
RE53 EQU (0x0<<21)
RE54 EQU (0x0<<22)
RE55 EQU (0x0<<23)
RE56 EQU (0x0<<24)
RE57 EQU (0x0<<25)
RE58 EQU (0x0<<26)
RE59 EQU (0x0<<27)
RE60 EQU (0x0<<28)
RE61 EQU (0x0<<29)
RE62 EQU (0x0<<30)
RE63 EQU (0x0<<31)
;// GRER2 0x40e00038 if RE[x]=0,Disable rising-edge detect enable.
;//if RE[x]=1,Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
RE64 EQU (0x0<<0)
RE65 EQU (0x0<<1)
RE66 EQU (0x0<<2)
RE67 EQU (0x0<<3)
RE68 EQU (0x0<<4)
RE69 EQU (0x0<<5)
RE70 EQU (0x0<<6)
RE71 EQU (0x0<<7)
RE72 EQU (0x0<<8)
RE73 EQU (0x0<<9)
RE74 EQU (0x0<<10)
RE75 EQU (0x0<<11)
RE76 EQU (0x0<<12)
RE77 EQU (0x0<<13)
RE78 EQU (0x0<<14)
RE79 EQU (0x0<<15)
RE80 EQU (0x0<<16)
RE81 EQU (0x0<<17)
RE82 EQU (0x0<<18)
RE83 EQU (0x0<<19)
RE84 EQU (0x0<<20)
;// GFER0 0x40e0003c if FE[x]=0,Disable falling-edge detect enable
;//if FE[x]=1,Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
FE0 EQU (0x0<<0)
FE1 EQU (0x0<<1)
FE2 EQU (0x0<<2)
FE3 EQU (0x0<<3)
FE4 EQU (0x0<<4)
FE5 EQU (0x0<<5)
FE6 EQU (0x0<<6)
FE7 EQU (0x0<<7)
FE8 EQU (0x0<<8)
FE9 EQU (0x0<<9)
FE10 EQU (0x0<<10)
FE11 EQU (0x0<<11)
FE12 EQU (0x0<<12)
FE13 EQU (0x0<<13)
FE14 EQU (0x0<<14)
FE15 EQU (0x0<<15)
FE16 EQU (0x0<<16)
FE17 EQU (0x0<<17)
FE18 EQU (0x0<<18)
FE19 EQU (0x0<<19)
FE20 EQU (0x0<<20)
FE21 EQU (0x0<<21)
FE22 EQU (0x0<<22)
FE23 EQU (0x0<<23)
FE24 EQU (0x0<<24)
FE25 EQU (0x0<<25)
FE26 EQU (0x0<<26)
FE27 EQU (0x0<<27)
FE28 EQU (0x0<<28)
FE29 EQU (0x0<<29)
FE30 EQU (0x0<<30)
FE31 EQU (0x0<<31)
;// GFER1 0x40e00040 if FE[x]=0,Disable falling-edge detect enable
;//if FE[x]=1,Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
FE32 EQU (0x0<<0)
FE33 EQU (0x0<<1)
FE34 EQU (0x0<<2)
FE35 EQU (0x0<<3)
FE36 EQU (0x0<<4)
FE37 EQU (0x0<<5)
FE38 EQU (0x0<<6)
FE39 EQU (0x0<<7)
FE40 EQU (0x0<<8)
FE41 EQU (0x0<<9)
FE42 EQU (0x0<<10)
FE43 EQU (0x0<<11)
FE44 EQU (0x0<<12)
FE45 EQU (0x0<<13)
FE46 EQU (0x0<<14)
FE47 EQU (0x0<<15)
FE48 EQU (0x0<<16)
FE49 EQU (0x0<<17)
FE50 EQU (0x0<<18)
FE51 EQU (0x0<<19)
FE52 EQU (0x0<<20)
FE53 EQU (0x0<<21)
FE54 EQU (0x0<<22)
FE55 EQU (0x0<<23)
FE56 EQU (0x0<<24)
FE57 EQU (0x0<<25)
FE58 EQU (0x0<<26)
FE59 EQU (0x0<<27)
FE60 EQU (0x0<<28)
FE61 EQU (0x0<<29)
FE62 EQU (0x0<<30)
FE63 EQU (0x0<<31)
;// GFER2 0x40e00044 if FE[x]=0,Disable falling-edge detect enable
;//if FE[x]=1,Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
FE64 EQU (0x0<<0)
FE65 EQU (0x0<<1)
FE66 EQU (0x0<<2)
FE67 EQU (0x0<<3)
FE68 EQU (0x0<<4)
FE69 EQU (0x0<<5)
FE70 EQU (0x0<<6)
FE71 EQU (0x0<<7)
FE72 EQU (0x0<<8)
FE73 EQU (0x0<<9)
FE74 EQU (0x0<<10)
FE75 EQU (0x0<<11)
FE76 EQU (0x0<<12)
FE77 EQU (0x0<<13)
FE78 EQU (0x0<<14)
FE79 EQU (0x0<<15)
FE80 EQU (0x0<<16)
FE81 EQU (0x0<<17)
FE82 EQU (0x0<<18)
FE83 EQU (0x0<<19)
FE84 EQU (0x0<<20)
;// GEDR0 0x40e00048 if ED[x]=0 (READ) No edge detect has occurred on pin as specified in GRER and/or GFER. (Write)No effect.
;// if ED[x]=1 (READ) Edge detect has occurred on pin as specified in GRER and/or GFER. (Write) Clear edge detect status field.
ED0 EQU (0x0<<0)
ED1 EQU (0x0<<1)
ED2 EQU (0x0<<2)
ED3 EQU (0x0<<3)
ED4 EQU (0x0<<4)
ED5 EQU (0x0<<5)
ED6 EQU (0x0<<6)
ED7 EQU (0x0<<7)
ED8 EQU (0x0<<8)
ED9 EQU (0x0<<9)
ED10 EQU (0x0<<10)
ED11 EQU (0x0<<11)
ED12 EQU (0x0<<12)
ED13 EQU (0x0<<13)
ED14 EQU (0x0<<14)
ED15 EQU (0x0<<15)
ED16 EQU (0x0<<16)
ED17 EQU (0x0<<17)
ED18 EQU (0x0<<18)
ED19 EQU (0x0<<19)
ED20 EQU (0x0<<20)
ED21 EQU (0x0<<21)
ED22 EQU (0x0<<22)
ED23 EQU (0x0<<23)
ED24 EQU (0x0<<24)
ED25 EQU (0x0<<25)
ED26 EQU (0x0<<26)
ED27 EQU (0x0<<27)
ED28 EQU (0x0<<28)
ED29 EQU (0x0<<29)
ED30 EQU (0x0<<30)
ED31 EQU (0x0<<31)
;// GEDR1 0x40e0004c if ED[x]=0 (READ) No edge detect has occurred on pin as specified in GRER and/or GFER. (Write)No effect.
;// if ED[x]=1 (READ) Edge detect has occurred on pin as specified in GRER and/or GFER. (Write) Clear edge detect status field.
ED32 EQU (0x0<<0)
ED33 EQU (0x0<<1)
ED34 EQU (0x0<<2)
ED35 EQU (0x0<<3)
ED36 EQU (0x0<<4)
ED37 EQU (0x0<<5)
ED38 EQU (0x0<<6)
ED39 EQU (0x0<<7)
ED40 EQU (0x0<<8)
ED41 EQU (0x0<<9)
ED42 EQU (0x0<<10)
ED43 EQU (0x0<<11)
ED44 EQU (0x0<<12)
ED45 EQU (0x0<<13)
ED46 EQU (0x0<<14)
ED47 EQU (0x0<<15)
ED48 EQU (0x0<<16)
ED49 EQU (0x0<<17)
ED50 EQU (0x0<<18)
ED51 EQU (0x0<<19)
ED52 EQU (0x0<<20)
ED53 EQU (0x0<<21)
ED54 EQU (0x0<<22)
ED55 EQU (0x0<<23)
ED56 EQU (0x0<<24)
ED57 EQU (0x0<<25)
ED58 EQU (0x0<<26)
ED59 EQU (0x0<<27)
ED60 EQU (0x0<<28)
ED61 EQU (0x0<<29)
ED62 EQU (0x0<<30)
ED63 EQU (0x0<<31)
;// GEDR2 0x40e00050 if ED[x]=0 (READ) No edge detect has occurred on pin as specified in GRER and/or GFER. (Write)No effect.
;// if ED[x]=1 (READ) Edge detect has occurred on pin as specified in GRER and/or GFER. (Write) Clear edge detect status field.
ED64 EQU (0x0<<0)
ED65 EQU (0x0<<1)
ED66 EQU (0x0<<2)
ED67 EQU (0x0<<3)
ED68 EQU (0x0<<4)
ED69 EQU (0x0<<5)
ED70 EQU (0x0<<6)
ED71 EQU (0x0<<7)
ED72 EQU (0x0<<8)
ED73 EQU (0x0<<9)
ED74 EQU (0x0<<10)
ED75 EQU (0x0<<11)
ED76 EQU (0x0<<12)
ED77 EQU (0x0<<13)
ED78 EQU (0x0<<14)
ED79 EQU (0x0<<15)
ED80 EQU (0x0<<16)
ED81 EQU (0x0<<17)
ED82 EQU (0x0<<18)
ED83 EQU (0x0<<19)
ED84 EQU (0x0<<20)
end
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