📄 davincievm.c
字号:
/*
* Copyright 2005 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*
* Not for distribution.
*/
/*
* Board Setup for DaVinci EVM ( ARM & DSP )
*
*/
#include "davincievm.h"
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_pll_on( pll_number, clock_source, pll_multipler, ) *
* *
* *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_pll_on( Uint16 pll_number, Uint16 clock_source, Uint16 pll_multipler )
{
volatile Uint32* pll_ctl;
volatile Uint32* pll_pllm;
pll_number &= 0x00000001; // Range [0=PLL1 1=PLL2]
clock_source &= 0x00000001; // Range [0:OSCIN 1:CLKIN]
pll_multipler -= 1;
pll_multipler &= 0x0000003F; // Range [1-64]
if ( pll_number == 0 ) // For PLL1
{
pll_ctl = ( volatile Uint32* )PLL1_PLLCTL;
pll_pllm = ( volatile Uint32* )PLL1_PLLM;
}
else // For PLL2
{
pll_ctl = ( volatile Uint32* )PLL2_PLLCTL;
pll_pllm = ( volatile Uint32* )PLL2_PLLM;
}
*pll_ctl &= 0xFFFFFEFF;
*pll_ctl |= ( clock_source << 8 ); // Select clock mode
*pll_ctl &= 0xFFFFFFDF; // Set PLLENSRC '0', PLL Enable( PLLEN ) selection is controlled through MMR
*pll_ctl &= 0xFFFFFFFE; // Put PLL in bypass mode
sw_wait( 0x20 ); // wait for PLL o switch to bypass clock
*pll_ctl &= 0xFFFFFFF7; // Reset the PLL
*pll_ctl |= 0x00000010; // Disable the PLL
*pll_ctl &= 0xFFFFFFFD; // Power up the PLL
*pll_ctl &= 0xFFFFFFEF; // Enable the PLL from Disable Mode
/*
* Program PREDIV Reg, POSTDIV register and OSCDIV1 Reg
* 1. predvien_pi is set to '1' in DaVinci, NO Predivier in DaVinci
* 2. prediv_ratio_lock_pi is set to '1', RATIO field of PREDIV is locked
* 3. Set the PLLM Register
* 4. Dont program POSTDIV Register
*/
*pll_pllm = pll_multipler; // Set PLL multipler
/*
* GEM, ARM, VBUS, CFG etc CLOCKS are fixed, dont program the registers
*/
sw_wait( 0x100 ); // Wait for PLL to Reset properly => PLL reset Time
*pll_ctl |= 0x00000008; // Bring PLL out of Reset
sw_wait( 0x1000 ); // Wait for > 2000 MXI clock for PLL to LOCK
*pll_ctl |= 0x00000001; // Enable the PLL Bit of PLLCTL
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_psc_on( domain, id ) *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_psc_on( Uint32 domain, Uint32 id )
{
volatile Uint32* mdstat = ( Uint32* )( PSC_MDSTAT_BASE + 4 * id );
volatile Uint32* mdctl = ( Uint32* )( PSC_MDCTL_BASE + 4 * id );
*mdctl |= 0x0003; // Set PowerDomain to turn on
if ( ( PSC_PDSTAT & 0x0001 ) == 0 )
{
PSC_PDCTL1 |= 0x0001;
PSC_PTCMD = 1 << domain; // Start state transtion on ALWAYSON power domain
while ( ( ( ( PSC_EPCPR >> domain ) & 1 ) == 0 ) ); // Wait for operation to complete
PSC_PDCTL1 |= 0x0100;
while( ! ( ( ( PSC_PTSTAT >> domain ) & 1 ) == 0 ) );// Wait for operation to complete
}
else
{
PSC_PTCMD = 1 << domain;
while( ! ( ( ( PSC_PTSTAT >> domain ) & 1 ) == 0 ) );
}
while( ! ( ( *mdstat & 0x001F ) == 0x3 ) );
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_psc_all_on( domain, id ) *
* *
* This turns on all clocks in ALWAYSON and DSP power domains. *
* Note this function assumes that the Power Domains are already on. *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_psc_all_on( )
{
Int16 i;
for( i = 0 ; i < 41 ; i++ )
{
*( Uint32* )( PSC_MDCTL_BASE+ 4 * i ) |= 0x0003;// Enable all 41 power domains
}
/*
* Set the following PSC_MDCTL[i].EMURSTIE to 0x1
*/
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 1 ) |= 0x0200; // VPSS MMR
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 5 ) |= 0x0200; // EMAC
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 6 ) |= 0x0200; // EMAC Wrapper
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 7 ) |= 0x0200; // MDIO
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 9 ) |= 0x0200; // USB
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 10 ) |= 0x0200; // ATA/CF
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 11 ) |= 0x0200; // VLYNQ
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 12 ) |= 0x0200; // HPI
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 13 ) |= 0x0200; // DDR2
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 14 ) |= 0x0200; // AEMIF
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 15 ) |= 0x0200; // MMC/SD
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 16 ) |= 0x0200; // MemoryStick
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 17 ) |= 0x0200; // ASP
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 26 ) |= 0x0200; // GPIO
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 40 ) |= 0x0200; // IMCOP
PSC_PTCMD = 0x0001; // Start state transtion on ALWAYSON power domain
while( ! ( ( PSC_PTSTAT & 0x0001 ) == 0 ) ); // Wait for operation to complete
PSC_PTCMD = 0x0002; // Start state transtion on DSP power domain
while( ! ( ( PSC_PTSTAT & 0x0002 ) == 0 ) ); // Wait for operation to complete
/*
* Clear the following PSC_MDCTL[i].EMURSTIE to 0x0
*/
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 1 ) &= 0x0003; // VPSS MMR
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 5 ) &= 0x0003; // EMAC
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 6 ) &= 0x0003; // EMAC Wrapper
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 7 ) &= 0x0003; // MDIO
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 9 ) &= 0x0003; // USB
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 10 ) &= 0x0003; // ATA/CF
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 11 ) &= 0x0003; // VLYNQ
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 12 ) &= 0x0003; // HPI
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 13 ) &= 0x0003; // DDR2
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 14 ) &= 0x0003; // AEMIF
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 15 ) &= 0x0003; // MMC/SD
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 16 ) &= 0x0003; // MemoryStick
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 17 ) &= 0x0003; // ASP
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 26 ) &= 0x0003; // GPIO
*( Uint32* )( PSC_MDCTL_BASE+ 4 * 40 ) &= 0x0003; // IMCOP
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_pin_mux_on( ) *
* *
* *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_pin_mux_on( Uint32 pinmux0, Uint32 pinmux1 )
{
PINMUX0 |= pinmux0;
PINMUX1 |= pinmux1;
return 0;
}
Int16 DAVINCIEVM_pin_mux_off( Uint32 pinmux0, Uint32 pinmux1 )
{
PINMUX0 &= ~pinmux0;
PINMUX1 &= ~pinmux1;
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_aemif_init( ) *
* *
* *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_aemif_init( Uint32 acfg2, Uint32 acfg3, Uint32 acfg4, Uint32 acfg5 )
{
AEMIF_ACFG2 = acfg2;
AEMIF_ACFG3 = acfg3;
AEMIF_ACFG4 = acfg4;
AEMIF_ACFG5 = acfg5;
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_ddr_init( ) *
* *
* *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_ddr_init( )
{
/*
* DDR Initialization @ 135MHz
*/
DDRCTL = 0x50006435; // put PHY in reset
sw_wait( 100 );
DDRCTL = 0x50006405; // Program PHY Control Register
SDCFG = 0x00008632; // Program SDRAM Bank Config Register
SDTIM0 = 0x229229c9; // Program SDRAM Timing Control Register
SDTIM1 = 0x0012c722;
SDCFG = 0x00000632; // Program SDRAM Bank Config Register
SDREF = 0x0000041d; // Program SDRAM Refresh Control Register
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* sw_wait( delay ) *
* *
* Wait in a software loop *
* *
* ------------------------------------------------------------------------ */
void sw_wait( Uint32 delay )
{
Uint32 i;
for ( i = 0 ; i < delay ; i++ );
}
void sw_waitusec( Uint32 usec )
{
sw_wait( usec * 1000 );
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -