is_en.txt

这是一个用java编的windlx模拟器

EduMIPS64 INSTRUCTION SET
=========================

Here's a quick reference guide to the EduMIPS64 Instruction Set. Some 
descriptions are taken from the MIPS64 Manual. Please let us know if it is a 
problem, and we will remove them.

ADD Instruction

Syntax: ADD rd, rs, rt
Description: 
            To add 32-bit integers. If overflow occurs, then trap.
            
ADDI Instruction

Syntax: ADDI rt, rs, immediate
Description: 
            To add a constant to a 32-bit integer. If overflow occurs, then trap.

ADDU Instruction

Syntax: ADDU rd, rs, rt
Description: rd = rs + rt
            To add 32-bit integers
            The 32-bit word value in GPR rt is added to the 32-bit value 
            in GPR rs and the 32-bit arithmetic result is placed into GPR rd.
            No Integer Overflow exception occurs under any circumstances.
            
ADDIU Instruction

Syntax: ADDIU rt, rs, immediate
Description: 
            To add a constant to a 32-bit integer
            The 16-bit signed immediate is added to the 32-bit value 
            in GPR rs and the 32-bit arithmetic result is placed into
            GPR rt. No Integer Overflow exception occurs under any circumstances.
			
AND Instruction

Syntax: AND rd, rs, rt 
Description: rd = rs and rt
            Does a bitwise logical AND, the contents of GPR rs are combined 
            with the contents of GPR rt in a bitwise logical AND operation.
            The result is placed into GPR rd.
            
            
ANDI Instruction

Syntax: ANDI rt, rs, immediate
Description: rt = rs AND immediate
            Does a bitwise logical AND with a constant
            The 16-bit immediate is zero-extended to the left and combined 
            with the contents of GPR rs in a bitwise logical AND
            operation. The result is placed into GPR rt.
            
B Instruction

Syntax: B offset
Description: Jumps inconditionally to offset

BEQ Instruction

Syntax: BEQ rs, rt, offset
Description: if rs = rt then branch
            To compare GPRs then do a PC-relative conditional branch
            
BEQZ Instruction

Syntax: BEQZ rs, offset
Description: if rs == 0 then branch
            To test a GPR then do a PC-relative conditional branch
             
BGEZ Instruction

Syntax: BGEZ rs, offset
Description: if rs >= 0 then branch
            Does a PC-relative branch to offset if rs >= 0

BNE Instruction

Syntax: BNE rt, rs, immediate
Description: if rs != rt then branch
            To compare GPRs then do a PC-relative conditional branch
            
BNEZ Instruction

Syntax: BNEZ rs, offset
Description: if rs != 0 then branch  
            To test a GPR then do a PC-relative conditional branch
            
DADD Instruction

Syntax: DADD rd, rs, rt
Description: 
            To add 64-bit integers. If overflow occurs, then trap.
            
DADDI Instruction

Syntax: DADDI rt, rs, immediate
Description: 
            To add a constant to a 64-bit integer. If overflow occurs, then trap.

DADDU Instruction

Syntax: DADDU rd, rs, rt
Description: rd = rs + rt
            To add 64-bit integers
            The 64-bit doubleword value in GPR rt is added to the 64-bit value 
            in GPR rs and the 64-bit arithmetic result is placed into GPR rd.
            No Integer Overflow exception occurs under any circumstances.
            
DADDIU Instruction

Syntax: DADDIU rt, rs, immediate
Description: 
            To add a constant to a 64-bit integer
            The 16-bit signed immediate is added to the 64-bit value 
            in GPR rs and the 64-bit arithmetic result is placed into
            GPR rt. No Integer Overflow exception occurs under any circumstances.

DDIV Instruction

Syntax: DDIV rs, rt
Description: (LO, HI) = rs / rt
            To divide 64-bit signed integers
            The 64-bit doubleword in GPR rs is divided by the 64-bit 
            doubleword in GPR rt, treating both operands as signed values.
            The 64-bit quotient is placed into special register LO and the 
            64-bit remainder is placed into special register HI.
            No arithmetic exception occurs under any circumstances.

DDIVU Instruction

Syntax: DDIVU rs, rt
Description: (LO, HI) = rs / rt
            To divide 64-bit unsigned integers
            The 64-bit doubleword in GPR rs is divided by the 64-bit 
            doubleword in GPR rt, treating both operands as unsigned values.
            The 64-bit quotient is placed into special register LO and the 
            64-bit remainder is placed into special register HI.
            No arithmetic exception occurs under any circumstances.
            
DIV Instruction

Syntax: DIV rs, rt
Description: (LO, HI) = rs / rt
            To divide 32-bit signed integers
            The 32-bit word in GPR rs is divided by the 32-bit 
            word in GPR rt, treating both operands as signed values.
            The 32-bit quotient is placed into special register LO and the 
            32-bit remainder is placed into special register HI.
            No arithmetic exception occurs under any circumstances.

DIVU Instruction

Syntax: DIVU rs, rt
Description: (LO, HI) = rs / rt
            To divide 32-bit unsigned integers
            The 32-bit word in GPR rs is divided by the 32-bit 
            word in GPR rt, treating both operands as unsigned values.
            The 32-bit quotient is placed into special register LO and the 
            32-bit remainder is placed into special register HI.
            No arithmetic exception occurs under any circumstances.
			
DMULT Instruction

Syntax: DMULT rs, rt
Description: (LO) = rs * rt
           To divide 64-bit signed integers
           The 64-bit doubleword value in GPR rt is multiplied by the 64-bit 
           value in GPR rs, treating both operands as signed values.

DMULTU Instruction

Syntax: DMULTU rs, rt
Description: (LO) = rs * rt
           To divide 64-bit unsigned integers
           The 64-bit doubleword value in GPR rt is multiplied by the 64-bit 
           value in GPR rs, treating both operands as unsigned values.
           
DSLL Instruction

Syntax: DSLL rd, rt, sa
Description: 
            To execute a left-shift of a doubleword by a fixed amount 0 to 31 bits
            The 64-bit doubleword contents of GPR rt are shifted left, 
            inserting zeros into the emptied bits; the result is placed in GPR rd. 
            The bit-shift amount in the range 0 to 31 is specified by sa.
            
DSLLV Instruction

Syntax: DSLLV rd, rt, rs
Description: 
            To execute a left-shift of a doubleword by a variable number of bits.
            The 64-bit doubleword contents of GPR rt are shifted left, inserting 
            zeros into the emptied bits; the result is placed in GPR rd.
            The bit-shift amount is specified by the low-order 6 bits in GPR rs (the value is unsigned).
            
DSRA Instruction

Format: DSRA rd, rt, sa
Description: 
            To execute an arithmetic right-shift of a doubleword 
            by a fixed amount