dzxs.tan.qmsg

altera 中基于NIOS软核系统的16点阵汉字显示程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register SHIKONG:u1\|jishu\[18\] register SHIKONG:u1\|s\[1\] 138.68 MHz 7.211 ns Internal " "Info: Clock \"clk\" has Internal fmax of 138.68 MHz between source register \"SHIKONG:u1\|jishu\[18\]\" and destination register \"SHIKONG:u1\|s\[1\]\" (period= 7.211 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.950 ns + Longest register register " "Info: + Longest register to register delay is 6.950 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SHIKONG:u1\|jishu\[18\] 1 REG LC_X11_Y2_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y2_N8; Fanout = 4; REG Node = 'SHIKONG:u1\|jishu\[18\]'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "" { SHIKONG:u1|jishu[18] } "NODE_NAME" } "" } } { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.590 ns) 1.363 ns SHIKONG:u1\|reduce_nor~284 2 COMB LC_X11_Y2_N2 1 " "Info: 2: + IC(0.773 ns) + CELL(0.590 ns) = 1.363 ns; Loc. = LC_X11_Y2_N2; Fanout = 1; COMB Node = 'SHIKONG:u1\|reduce_nor~284'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "1.363 ns" { SHIKONG:u1|jishu[18] SHIKONG:u1|reduce_nor~284 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.435 ns) + CELL(0.590 ns) 3.388 ns SHIKONG:u1\|reduce_nor~285 3 COMB LC_X10_Y1_N9 1 " "Info: 3: + IC(1.435 ns) + CELL(0.590 ns) = 3.388 ns; Loc. = LC_X10_Y1_N9; Fanout = 1; COMB Node = 'SHIKONG:u1\|reduce_nor~285'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "2.025 ns" { SHIKONG:u1|reduce_nor~284 SHIKONG:u1|reduce_nor~285 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.590 ns) 4.410 ns SHIKONG:u1\|reduce_nor~0 4 COMB LC_X10_Y1_N7 28 " "Info: 4: + IC(0.432 ns) + CELL(0.590 ns) = 4.410 ns; Loc. = LC_X10_Y1_N7; Fanout = 28; COMB Node = 'SHIKONG:u1\|reduce_nor~0'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "1.022 ns" { SHIKONG:u1|reduce_nor~285 SHIKONG:u1|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.673 ns) + CELL(0.867 ns) 6.950 ns SHIKONG:u1\|s\[1\] 5 REG LC_X11_Y2_N9 18 " "Info: 5: + IC(1.673 ns) + CELL(0.867 ns) = 6.950 ns; Loc. = LC_X11_Y2_N9; Fanout = 18; REG Node = 'SHIKONG:u1\|s\[1\]'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "2.540 ns" { SHIKONG:u1|reduce_nor~0 SHIKONG:u1|s[1] } "NODE_NAME" } "" } } { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.637 ns 37.94 % " "Info: Total cell delay = 2.637 ns ( 37.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.313 ns 62.06 % " "Info: Total interconnect delay = 4.313 ns ( 62.06 % )" {  } {  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "6.950 ns" { SHIKONG:u1|jishu[18] SHIKONG:u1|reduce_nor~284 SHIKONG:u1|reduce_nor~285 SHIKONG:u1|reduce_nor~0 SHIKONG:u1|s[1] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "6.950 ns" { SHIKONG:u1|jishu[18] SHIKONG:u1|reduce_nor~284 SHIKONG:u1|reduce_nor~285 SHIKONG:u1|reduce_nor~0 SHIKONG:u1|s[1] } { 0.000ns 0.773ns 1.435ns 0.432ns 1.673ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.432 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 38 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 38; CLK Node = 'clk'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "" { clk } "NODE_NAME" } "" } } { "dzxs.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.246 ns) + CELL(0.711 ns) 7.432 ns SHIKONG:u1\|s\[1\] 2 REG LC_X11_Y2_N9 18 " "Info: 2: + IC(5.246 ns) + CELL(0.711 ns) = 7.432 ns; Loc. = LC_X11_Y2_N9; Fanout = 18; REG Node = 'SHIKONG:u1\|s\[1\]'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "5.957 ns" { clk SHIKONG:u1|s[1] } "NODE_NAME" } "" } } { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns 29.41 % " "Info: Total cell delay = 2.186 ns ( 29.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.246 ns 70.59 % " "Info: Total interconnect delay = 5.246 ns ( 70.59 % )" {  } {  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.432 ns" { clk SHIKONG:u1|s[1] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.432 ns" { clk clk~out0 SHIKONG:u1|s[1] } { 0.000ns 0.000ns 5.246ns } { 0.000ns 1.475ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.432 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 38 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 38; CLK Node = 'clk'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "" { clk } "NODE_NAME" } "" } } { "dzxs.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.246 ns) + CELL(0.711 ns) 7.432 ns SHIKONG:u1\|jishu\[18\] 2 REG LC_X11_Y2_N8 4 " "Info: 2: + IC(5.246 ns) + CELL(0.711 ns) = 7.432 ns; Loc. = LC_X11_Y2_N8; Fanout = 4; REG Node = 'SHIKONG:u1\|jishu\[18\]'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "5.957 ns" { clk SHIKONG:u1|jishu[18] } "NODE_NAME" } "" } } { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns 29.41 % " "Info: Total cell delay = 2.186 ns ( 29.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.246 ns 70.59 % " "Info: Total interconnect delay = 5.246 ns ( 70.59 % )" {  } {  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.432 ns" { clk SHIKONG:u1|jishu[18] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.432 ns" { clk clk~out0 SHIKONG:u1|jishu[18] } { 0.000ns 0.000ns 5.246ns } { 0.000ns 1.475ns 0.711ns } } }  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.432 ns" { clk SHIKONG:u1|s[1] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.432 ns" { clk clk~out0 SHIKONG:u1|s[1] } { 0.000ns 0.000ns 5.246ns } { 0.000ns 1.475ns 0.711ns } } } { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.432 ns" { clk SHIKONG:u1|jishu[18] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.432 ns" { clk clk~out0 SHIKONG:u1|jishu[18] } { 0.000ns 0.000ns 5.246ns } { 0.000ns 1.475ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 47 -1 0 } }  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "6.950 ns" { SHIKONG:u1|jishu[18] SHIKONG:u1|reduce_nor~284 SHIKONG:u1|reduce_nor~285 SHIKONG:u1|reduce_nor~0 SHIKONG:u1|s[1] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "6.950 ns" { SHIKONG:u1|jishu[18] SHIKONG:u1|reduce_nor~284 SHIKONG:u1|reduce_nor~285 SHIKONG:u1|reduce_nor~0 SHIKONG:u1|s[1] } { 0.000ns 0.773ns 1.435ns 0.432ns 1.673ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.867ns } } } { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.432 ns" { clk SHIKONG:u1|s[1] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.432 ns" { clk clk~out0 SHIKONG:u1|s[1] } { 0.000ns 0.000ns 5.246ns } { 0.000ns 1.475ns 0.711ns } } } { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.432 ns" { clk SHIKONG:u1|jishu[18] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.432 ns" { clk clk~out0 SHIKONG:u1|jishu[18] } { 0.000ns 0.000ns 5.246ns } { 0.000ns 1.475ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk hang\[12\] WEIXUAN:u2\|a\[3\] 18.064 ns register " "Info: tco from clock \"clk\" to destination pin \"hang\[12\]\" through register \"WEIXUAN:u2\|a\[3\]\" is 18.064 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.447 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 38 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 38; CLK Node = 'clk'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "" { clk } "NODE_NAME" } "" } } { "dzxs.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.261 ns) + CELL(0.711 ns) 7.447 ns WEIXUAN:u2\|a\[3\] 2 REG LC_X17_Y1_N5 16 " "Info: 2: + IC(5.261 ns) + CELL(0.711 ns) = 7.447 ns; Loc. = LC_X17_Y1_N5; Fanout = 16; REG Node = 'WEIXUAN:u2\|a\[3\]'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "5.972 ns" { clk WEIXUAN:u2|a[3] } "NODE_NAME" } "" } } { "WEIXUAN.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/WEIXUAN.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns 29.35 % " "Info: Total cell delay = 2.186 ns ( 29.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.261 ns 70.65 % " "Info: Total interconnect delay = 5.261 ns ( 70.65 % )" {  } {  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.447 ns" { clk WEIXUAN:u2|a[3] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.447 ns" { clk clk~out0 WEIXUAN:u2|a[3] } { 0.000ns 0.000ns 5.261ns } { 0.000ns 1.475ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "WEIXUAN.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/WEIXUAN.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.393 ns + Longest register pin " "Info: + Longest register to pin delay is 10.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns WEIXUAN:u2\|a\[3\] 1 REG LC_X17_Y1_N5 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y1_N5; Fanout = 16; REG Node = 'WEIXUAN:u2\|a\[3\]'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "" { WEIXUAN:u2|a[3] } "NODE_NAME" } "" } } { "WEIXUAN.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/WEIXUAN.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.774 ns) + CELL(0.590 ns) 2.364 ns XIANSHI:u3\|Mux~466 2 COMB LC_X15_Y2_N7 6 " "Info: 2: + IC(1.774 ns) + CELL(0.590 ns) = 2.364 ns; Loc. = LC_X15_Y2_N7; Fanout = 6; COMB Node = 'XIANSHI:u3\|Mux~466'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "2.364 ns" { WEIXUAN:u2|a[3] XIANSHI:u3|Mux~466 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.590 ns) 3.390 ns XIANSHI:u3\|Q\[2\]~2136 3 COMB LC_X15_Y2_N8 2 " "Info: 3: + IC(0.436 ns) + CELL(0.590 ns) = 3.390 ns; Loc. = LC_X15_Y2_N8; Fanout = 2; COMB Node = 'XIANSHI:u3\|Q\[2\]~2136'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "1.026 ns" { XIANSHI:u3|Mux~466 XIANSHI:u3|Q[2]~2136 } "NODE_NAME" } "" } } { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.590 ns) 4.680 ns XIANSHI:u3\|Q\[11\]~2156 4 COMB LC_X15_Y2_N2 2 " "Info: 4: + IC(0.700 ns) + CELL(0.590 ns) = 4.680 ns; Loc. = LC_X15_Y2_N2; Fanout = 2; COMB Node = 'XIANSHI:u3\|Q\[11\]~2156'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "1.290 ns" { XIANSHI:u3|Q[2]~2136 XIANSHI:u3|Q[11]~2156 } "NODE_NAME" } "" } } { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.590 ns) 6.405 ns XIANSHI:u3\|Q\[12\]~2151 5 COMB LC_X15_Y1_N9 1 " "Info: 5: + IC(1.135 ns) + CELL(0.590 ns) = 6.405 ns; Loc. = LC_X15_Y1_N9; Fanout = 1; COMB Node = 'XIANSHI:u3\|Q\[12\]~2151'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "1.725 ns" { XIANSHI:u3|Q[11]~2156 XIANSHI:u3|Q[12]~2151 } "NODE_NAME" } "" } } { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(2.108 ns) 10.393 ns hang\[12\] 6 PIN PIN_67 0 " "Info: 6: + IC(1.880 ns) + CELL(2.108 ns) = 10.393 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'hang\[12\]'" {  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "3.988 ns" { XIANSHI:u3|Q[12]~2151 hang[12] } "NODE_NAME" } "" } } { "dzxs.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.468 ns 42.99 % " "Info: Total cell delay = 4.468 ns ( 42.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.925 ns 57.01 % " "Info: Total interconnect delay = 5.925 ns ( 57.01 % )" {  } {  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "10.393 ns" { WEIXUAN:u2|a[3] XIANSHI:u3|Mux~466 XIANSHI:u3|Q[2]~2136 XIANSHI:u3|Q[11]~2156 XIANSHI:u3|Q[12]~2151 hang[12] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "10.393 ns" { WEIXUAN:u2|a[3] XIANSHI:u3|Mux~466 XIANSHI:u3|Q[2]~2136 XIANSHI:u3|Q[11]~2156 XIANSHI:u3|Q[12]~2151 hang[12] } { 0.000ns 1.774ns 0.436ns 0.700ns 1.135ns 1.880ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.590ns 2.108ns } } }  } 0}  } { { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "7.447 ns" { clk WEIXUAN:u2|a[3] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "7.447 ns" { clk clk~out0 WEIXUAN:u2|a[3] } { 0.000ns 0.000ns 5.261ns } { 0.000ns 1.475ns 0.711ns } } } { "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" "" { Report "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs_cmp.qrpt" Compiler "dzxs" "UNKNOWN" "V1" "F:/VHDL练习/16乘16的点阵显示设计/db/dzxs.quartus_db" { Floorplan "F:/VHDL练习/16乘16的点阵显示设计/" "" "10.393 ns" { WEIXUAN:u2|a[3] XIANSHI:u3|Mux~466 XIANSHI:u3|Q[2]~2136 XIANSHI:u3|Q[11]~2156 XIANSHI:u3|Q[12]~2151 hang[12] } "NODE_NAME" } "" } } { "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii 5.0/bin/Technology_Viewer.qrui" "10.393 ns" { WEIXUAN:u2|a[3] XIANSHI:u3|Mux~466 XIANSHI:u3|Q[2]~2136 XIANSHI:u3|Q[11]~2156 XIANSHI:u3|Q[12]~2151 hang[12] } { 0.000ns 1.774ns 0.436ns 0.700ns 1.135ns 1.880ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.590ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 21 10:46:47 2007 " "Info: Processing ended: Fri Sep 21 10:46:47 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}