dzxs.qsf

altera 中基于NIOS软核系统的16点阵汉字显示程序

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		dzxs_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:32:14  SEPTEMBER 21, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name BDF_FILE Block1.bdf
set_global_assignment -name VHDL_FILE SHIKONG.vhd
set_global_assignment -name VHDL_FILE WEIXUAN.vhd
set_global_assignment -name VHDL_FILE XIANSHI.vhd
set_global_assignment -name VHDL_FILE "F:\\VHDL练习\\16乘16的点阵显示设计\\dzxs.vhd"
set_global_assignment -name VECTOR_WAVEFORM_FILE dzxs.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_123 -to clk
set_location_assignment PIN_40 -to hang[0]
set_location_assignment PIN_41 -to hang[1]
set_location_assignment PIN_42 -to hang[2]
set_location_assignment PIN_47 -to hang[3]
set_location_assignment PIN_48 -to hang[4]
set_location_assignment PIN_49 -to hang[5]
set_location_assignment PIN_50 -to hang[6]
set_location_assignment PIN_51 -to hang[7]
set_location_assignment PIN_52 -to hang[8]
set_location_assignment PIN_53 -to hang[9]
set_location_assignment PIN_54 -to hang[10]
set_location_assignment PIN_55 -to hang[11]
set_location_assignment PIN_67 -to hang[12]
set_location_assignment PIN_68 -to hang[13]
set_location_assignment PIN_69 -to hang[14]
set_location_assignment PIN_70 -to hang[15]
set_location_assignment PIN_71 -to lei[0]
set_location_assignment PIN_72 -to lei[1]
set_location_assignment PIN_58 -to lei[2]
set_location_assignment PIN_59 -to lei[3]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY dzxs

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"

# Assembler Assignments
# =====================
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY ON -section_id eda_simulation

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------