class.ptf

来自「altera NIOS软核系统中构建外接SRAM接口的例子」· PTF 代码 · 共 251 行

# Copyright(C) 2002-2003 Altera Corporation
CLASS sls_sram_16_bit
{
      ASSOCIATED_FILES 
      {
         Add_Program = "default";
         Edit_Program = "default";
         Generator_Program = "mk_sram.pl";
      }
      MODULE_DEFAULTS 
      {
         class = "sls_sram_16_bit";
         class_version = "1.0";
         iss_model_name = "altera_memory";
         HDL_INFO 
         {
# An interface to this memory requires no additional files
# in the target project directory.
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            sram_memory_size = "128";
            sram_memory_units = "1024";
            sram_data_width = "16";
         }
         SLAVE s1
         {
            PORT_WIRING 
            {
               PORT data
               {
                  width = "16";
                  is_shared = "1";
                  direction = "inout";
                  type = "data";
               }
               PORT address
               {
                  width = "16";
                  is_shared = "1";
                  direction = "input";
                  type = "address";
               }
               PORT read_n
               {
                  width = "1";
                  is_shared = "1";
                  direction = "input";
                  type = "read_n";
               }
               PORT write_n
               {
                  width = "1";
                  is_shared = "1";
                  direction = "input";
                  type = "write_n";
               }
               PORT be_n
               {
                  width = "2";
                  is_shared = "1";
                  direction = "input";
                  type = "byteenable_n";
               }
               PORT select_n
               {
                  width = "1";
                  is_shared = "0";
                  direction = "input";
                  type = "chipselect_n";
               }
            }
            SYSTEM_BUILDER_INFO 
            {
               Bus_Type = "avalon_tristate";
               Is_Memory_Device = "1";
               Address_Alignment = "dynamic";
               Data_Width = "16";
               Address_Width = "16";
               Has_IRQ = "0";
               IRQ_Number = "N/A";
               Read_Wait_States = "5"; 
               #"peripheral_controlled"; 
               #"0";
               Write_Wait_States = "5";
               #"peripheral_controlled"; 
               #"0";
               #Hold_Time = "half_clock";
               Base_Address = "--unknown--";
               Address_Span = "131072";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Is_Enabled = "1";
            Instantiate_In_System_Module = "0";
            Make_Memory_Model = "1";
            Default_Module_Name = "sram";
         }
      }
      USER_INTERFACE 
      {
         USER_LABELS 
         {
            name = "SLS_UP3_SRAM";
            technology = "UP3-Development Kit";
            license = "full";
         }
         LINKS
         {
            LINK Stratix_1S40_Manual
            {
               title="Manual for Nios 1s40 Stratix Board";
               url="http://www.altera.com/literature/manual/mnl_nios2_board_stratix_1s40.pdf";
            }
            LINK Stratix_1S40_Schematics
            {
               title="Schematics for Nios 1s40 Stratix Board";
               url="nios_stratix_1s40/nios_1s40_board_schematic.pdf";
            }
            LINK Stratix_1S10_Manual
            {
               title="Manual for Nios 1s10 Stratix Board";
               url="http://www.altera.com/literature/manual/mnl_nios2_board_stratix_1s10.pdf";
            }
            LINK Stratix_1S10_Schematics
            {
               title="Schematics for Nios 1s10 Stratix Board";
               url="nios_stratix_1s10/nios_1s10_board_schematic.pdf";
            }
            LINK Cyclone_Manual
            {
               title="Manual for Nios 1c20 Cyclone Board";
               url="http://www.altera.com/literature/manual/mnl_nios2_board_cyclone_1c20.pdf";
            }
            LINK Cyclone_Schematics
            {
               title="Schematics for Nios 1c20 Cyclone Board";
               url="nios_cyclone_1c20/nios_1c20_board_schematic.pdf";
            }
         }
         WIZARD_UI default
         {
            DEBUG{}
	    title = "SRAM (IS61C6416-10T chip) - {{ $MOD }}";
            CONTEXT 
            {
               WSA = "WIZARD_SCRIPT_ARGUMENTS";
               CONTENTS = "WIZARD_SCRIPT_ARGUMENTS/CONTENTS srec";
               SBI = "SLAVE s1/SYSTEM_BUILDER_INFO";
               MODULE_SBI = "SYSTEM_BUILDER_INFO";
               SPWA  = "SLAVE s1/PORT_WIRING/PORT address";
               SPWD  = "SLAVE s1/PORT_WIRING/PORT data";
               SPWBE = "SLAVE s1/PORT_WIRING/PORT be_n";
            }
# These assignments manage the continuous updating of values
# via the WSA, and some intermediate values.
            $$var_byte_count = "{{ $WSA/sram_memory_size * $WSA/sram_memory_units }}"; # aka address span
            $$var_word_count = "{{ $$var_byte_count * 8 / $WSA/sram_data_width }}";
            $$var_address_bits = "{{ ceil(log2($$var_word_count)) }}"; # 
# And now, poke in all those results to the right PTF spots
            $SBI/Address_Width = "{{ $$var_address_bits }}";
            $SBI/Address_Span = "{{ $$var_byte_count }}";
            $SBI/Data_Width = "{{ $WSA/sram_data_width }}";
            $SPWA/width = "{{ $$var_address_bits }}";
            $SPWD/width = "{{ $WSA/sram_data_width }}";
            $SPWBE/width = "{{ $WSA/sram_data_width / 8 }}";

        align = "left";
        PAGES main
        {
          select = 1;
#          align = "left";
          PAGE 1
          {
            title = "Attributes";
            GROUP 
            {
               align = "left";
               title = "Static RAM";
               spacing = 12;
               TEXT 
               {
                  title = 
                  "The ESDK Rev2 Board has one IS61C6416-10T SRAM chip arranged as <br>
                   64k 16-Bit Words (128KByte total address span). <br>"; 
               }

               GROUP 
               {
                  TEXT 
                  {
                     title = "Memory Size: ";
                  }
                  layout = "horizontal";
                  EDIT 
                  {
                     justify = "right";
                     DATA 
                     {
                        $WSA/sram_memory_size = "$";
                     }
                  }
                  COMBO 
                  {
                     DATA 
                     {
                        $WSA/sram_memory_units = "$";
                     }
                     ITEM 
                     {
                        title = "Bytes";
                        value = "1";
                     }
                     ITEM 
                     {
                        title = "kB";
                        value = "1024";
                     }
                  }
               }
               TEXT 
               {
                  title = "{{ $$var_address_bits }} Word Aligned Address Bits";
               }
            }
            GROUP simulation_model
            {
               title = "Generic Memory Model (Simulation Only)";
               align = "left";
               spacing = "0";
               CHECK
               {
                  title = 
                     "Include a functional memory model in the system testbench.";
                  tooltip =
                     "The model will auto-size to the declared SRAM profile.<br>When not selected, you must acquire a vendor memory model<br>and manually wire it into the testbench.";
                  DATA
                  {
                     $MODULE_SBI/Make_Memory_Model = $;
                  }
               }
            }

          }

        }
      }
   }
}