phy.h

Airgo agn1000系列 无线网卡驱动源码

#ifndef AGNX_PHY_H_
#define AGNX_PHY_H_

#include "agnx.h"

/* Transmission Managment Registers */
#define AGNX_TXM_BASE		0x0000
#define AGNX_TXM_CTL		0x0000	/* control register */
#define AGNX_TXM_ETMF		0x0004 /* enable transmission management functions */
#define AGNX_TXM_TXTEMP		0x0008 /* transmission template */
#define AGNX_TXM_RETRYSTAID	0x000c /* Retry Station ID */
#define AGNX_TXM_TIMESTAMPLO		0x0010	/* Timestamp Lo */
#define AGNX_TXM_TIMESTAMPHI		0x0014	/* Timestamp Hi */
#define AGNX_TXM_TXDELAY	0x0018  /* tx delay */
#define AGNX_TXM_TBTTLO		0x0020	/* tbtt Lo */	
#define AGNX_TXM_TBTTHI		0x0024	/* tbtt Hi */
#define AGNX_TXM_BEAINTER	0x0028 /* Beacon Interval */
#define AGNX_TXM_NAV		0x0030 /* NAV */
#define AGNX_TXM_CFPMDV		0x0034 /* CFP MDV */
#define AGNX_TXM_CFPERCNT	0x0038 /* CFP period count */
#define AGNX_TXM_PROBDELAY	0x003c /* probe delay */
#define AGNX_TXM_LISINTERCNT	0x0040 /* listen interval count */
#define AGNX_TXM_DTIMPERICNT	0x004c /* DTIM period count */

#define AGNX_TXM_BEACON_CTL	0x005c /* beacon control */

#define AGNX_TXM_SCHEMPCNT	0x007c /* schedule empty count */
#define AGNX_TXM_MAXTIMOUT	0x0084 /* max timeout exceed count */
#define AGNX_TXM_MAXCFPTIM	0x0088 /* max CF poll timeout count */
#define AGNX_TXM_MAXRXTIME	0x008c /* max RX timeout count */
#define AGNX_TXM_MAXACKTIM	0x0090	/* max ACK timeout count */
#define AGNX_TXM_DIF01		0x00a0 /* DIF 0-1 */
#define AGNX_TXM_DIF23		0x00a4 /* DIF 2-3 */
#define AGNX_TXM_DIF45		0x00a8 /* DIF 4-5 */
#define AGNX_TXM_DIF67		0x00ac /* DIF 6-7 */
#define AGNX_TXM_SIFSPIFS	0x00b0 /* SIFS/PIFS */
#define AGNX_TXM_TIFSEIFS	0x00b4 /* TIFS/EIFS */
#define AGNX_TXM_MAXCCACNTSLOT	0x00b8 /* max CCA count slot */
#define AGNX_TXM_SLOTLIMIT	0x00bc /* slot limit/1 msec limit */
#define AGNX_TXM_CFPOLLRXTIM	0x00f0 /* CF poll RX timeout count */
#define AGNX_TXM_CFACKT11B	0x00f4 /* CF ack timeout limit for 11b */
#define AGNX_TXM_CW0		0x0100 /* CW 0 */
#define AGNX_TXM_SLBEALIM0	0x0108 /* short/long beacon limit 0 */
#define AGNX_TXM_CW1		0x0120 /* CW 1 */
#define AGNX_TXM_SLBEALIM1	0x0128 /* short/long beacon limit 1 */
#define AGNX_TXM_CW2		0x0140 /* CW 2 */
#define AGNX_TXM_SLBEALIM2	0x0148 /* short/long beacon limit 2 */
#define AGNX_TXM_CW3		0x0160 /* CW 3 */
#define AGNX_TXM_SLBEALIM3	0x0168 /* short/long beacon limit 3 */
#define AGNX_TXM_CW4		0x0180 /* CW 4 */
#define AGNX_TXM_SLBEALIM4	0x0188 /* short/long beacon limit 4 */
#define AGNX_TXM_CW5		0x01a0 /* CW 5 */
#define AGNX_TXM_SLBEALIM5	0x01a8 /* short/long beacon limit 5 */
#define AGNX_TXM_CW6		0x01c0 /* CW 6 */
#define AGNX_TXM_SLBEALIM6	0x01c8 /* short/long beacon limit 6 */
#define AGNX_TXM_CW7		0x01e0 /* CW 7 */
#define AGNX_TXM_SLBEALIM7	0x01e8 /* short/long beacon limit 7 */
#define AGNX_TXM_BEACONTEMP     0x1000	/* beacon template */
#define AGNX_TXM_STAPOWTEMP	0x1a00 /*  Station Power Template */

/* Receive Management Control Registers */
#define AGNX_RXM_BASE		0x2000
#define AGNX_RXM_REQRATE	0x2000	/* requested rate */
#define AGNX_RXM_MACHI		0x2004	/* first 4 bytes of mac address */
#define AGNX_RXM_MACLO		0x2008	/* last 2 bytes of mac address */
#define AGNX_RXM_BSSIDHI	0x200c	/* bssid hi */
#define AGNX_RXM_BSSIDLO	0x2010	/* bssid lo */
#define AGNX_RXM_HASH_CMD_FLAG	0x2014	/* Flags for the RX Hash Command Default:0 */
#define AGNX_RXM_HASH_CMD_HIGH	0x2018	/* The High half of the Hash Command */
#define AGNX_RXM_HASH_CMD_LOW	0x201c	/* The Low half of the Hash Command */
#define AGNX_RXM_ROUTAB		0x2020	/* routing table */
#define		ROUTAB_SUBTYPE_SHIFT	24
#define		ROUTAB_TYPE_SHIFT	28
#define		ROUTAB_STATUS_SHIFT	30
#define		ROUTAB_RW_SHIFT		31
#define		ROUTAB_ROUTE_DROP	0xf00000 /* Drop */
#define		ROUTAB_ROUTE_CPU	0x400000 /* CPU */
#define		ROUTAB_ROUTE_ENCRY	0x500800 /* Encryption */
#define		ROUTAB_ROUTE_RFP	0x800000 /* RFP */

#define		ROUTAB_TYPE_MANAG	0x0 /* Management */
#define		ROUTAB_TYPE_CTL		0x1 /* Control */
#define		ROUTAB_TYPE_DATA	0x2 /* Data */

#define		ROUTAB_SUBTYPE_DATA		0x0
#define		ROUTAB_SUBTYPE_DATAACK		0x1
#define		ROUTAB_SUBTYPE_DATAPOLL		0x2
#define		ROUTAB_SUBTYPE_DATAPOLLACK	0x3	
#define		ROUTAB_SUBTYPE_NULL		0x4 /* NULL */
#define		ROUTAB_SUBTYPE_NULLACK		0x5
#define		ROUTAB_SUBTYPE_NULLPOLL		0x6
#define		ROUTAB_SUBTYPE_NULLPOLLACK	0x7
#define		ROUTAB_SUBTYPE_QOSDATA		0x8 /* QOS DATA */
#define		ROUTAB_SUBTYPE_QOSDATAACK	0x9  
#define		ROUTAB_SUBTYPE_QOSDATAPOLL	0xa
#define		ROUTAB_SUBTYPE_QOSDATAACKPOLL	0xb
#define		ROUTAB_SUBTYPE_QOSNULL		0xc
#define		ROUTAB_SUBTYPE_QOSNULLACK	0xd
#define		ROUTAB_SUBTYPE_QOSNULLPOLL	0xe
#define		ROUTAB_SUBTYPE_QOSNULLPOLLACK	0xf
#define AGNX_RXM_DELAY11	   0x2024	/* delay 11(AB) */
#define AGNX_RXM_SOF_CNT	   0x2028	/* SOF Count */
#define AGNX_RXM_FRAG_CNT	   0x202c	/* Fragment Count*/
#define AGNX_RXM_FCS_CNT	   0x2030	/* FCS Count */
#define AGNX_RXM_BSSID_MISS_CNT	   0x2034	/* BSSID Miss Count */
#define AGNX_RXM_PDU_ERR_CNT	   0x2038	/* PDU Error Count */
#define AGNX_RXM_DEST_MISS_CNT	   0x203C	/* Destination Miss Count */
#define AGNX_RXM_DROP_CNT	   0x2040	/* Drop Count */
#define AGNX_RXM_ABORT_CNT	   0x2044	/* Abort Count */
#define AGNX_RXM_RELAY_CNT	   0x2048	/* Relay Count */
#define AGNX_RXM_HASH_MISS_CNT	   0x204c	/* Hash Miss Count */
#define AGNX_RXM_SA_HI		   0x2050	/* Address of received packet Hi */
#define AGNX_RXM_SA_LO		   0x2054	/* Address of received packet Lo */
#define AGNX_RXM_HASH_DUMP_LST	   0x2100	/* Contains Hash Data */
#define AGNX_RXM_HASH_DUMP_MST	   0x2104	/* Contains Hash Data */
#define AGNX_RXM_HASH_DUMP_DATA    0x2108	/* The Station ID to dump */


/* Encryption Managment */
#define AGNX_ENCRY_BASE		0x2400
#define AGNX_ENCRY_WEPKEY0	0x2440 /* wep key #0 */
#define AGNX_ENCRY_WEPKEY1	0x2444 /* wep key #1 */
#define AGNX_ENCRY_WEPKEY2	0x2448 /* wep key #2 */
#define AGNX_ENCRY_WEPKEY3	0x244c /* wep key #3 */
#define AGNX_ENCRY_CCMRECTL	0x2460 /* ccm replay control */


/* Band Management Registers */
#define AGNX_BM_BASE		0x2c00
#define AGNX_BM_BMCTL		0x2c00  /* band management control */
#define AGNX_BM_TXWADDR		0x2c18  /* tx workqueue address start */
#define AGNX_BM_TXTOPEER	0x2c24	/* transmit to peers */
#define AGNX_BM_FPLHP		0x2c2c  /* free pool list head pointer */
#define AGNX_BM_FPLTP		0x2c30  /* free pool list tail pointer */
#define AGNX_BM_FPCNT		0x2c34  /* free pool count */
#define AGNX_BM_CIPDUWCNT	0x2c38  /* card interface pdu workqueue count */
#define AGNX_BM_SPPDUWCNT	0x2c3c  /* sp pdu workqueue count */
#define AGNX_BM_RFPPDUWCNT	0x2c40  /* rfp pdu workqueue count */
#define AGNX_BM_RHPPDUWCNT	0x2c44  /* rhp pdu workqueue count */
#define AGNX_BM_CIWQCTL		0x2c48 /* Card Interface WorkQueue Control */
#define AGNX_BM_CPUTXWCTL	0x2c50  /* cpu tx workqueue control */
#define AGNX_BM_CPURXWCTL	0x2c58  /* cpu rx workqueue control */
#define AGNX_BM_CPULWCTL	0x2c60 /* cpu low workqueue control */
#define AGNX_BM_CPUHWCTL	0x2c68 /* cpu high workqueue control */
#define AGNX_BM_SPTXWCTL	0x2c70 /* sp tx workqueue control */
#define AGNX_BM_SPRXWCTL	0x2c78 /* sp rx workqueue control */
#define AGNX_BM_RFPWCTL		0x2c80 /* RFP workqueue control */
#define AGNX_BM_MTSM		0x2c90 /* Multicast Transmit Station Mask */

/* Card Interface Registers (32bits) */
#define AGNX_CIR_BASE		0x3000	
#define AGNX_CIR_BLKCTL		0x3000	/* block control*/
#define		AGNX_STAT_TX	0x1
#define		AGNX_STAT_RX	0x2
#define		AGNX_STAT_X	0x4
/* Below two interrupt flags will be set by our but not CPU or the card */
#define		AGNX_STAT_TXD	0x10
#define		AGNX_STAT_TXM	0x20

#define AGNX_CIR_ADDRWIN	0x3004	/* Addressable Windows*/
#define AGNX_CIR_ENDIAN		0x3008  /* card endianness */
#define AGNX_CIR_SERIALITF	0x3020	/* serial interface */
#define AGNX_CIR_RXCFG		0x3040	/* receive config */
#define		ENABLE_RX_INTERRUPT 0x20
#define		RX_CACHE_LINE	    0x8	
/* the RX fragment length */
#define		FRAG_LEN_256	0x0 /* 256B */
#define		FRAG_LEN_512	0x1
#define		FRAG_LEN_1024	0x2
#define		FRAG_LEN_2048	0x3
#define		FRAG_BE		0x10
#define AGNX_CIR_RXCTL		0x3050	/* receive control */
/* memory address, chipside */
#define AGNX_CIR_RXCMSTART	0x3054	/* receive client memory start */
#define AGNX_CIR_RXCMEND	0x3058	/* receive client memory end */
/* memory address, pci */
#define AGNX_CIR_RXHOSTADDR	0x3060	/* receive hostside address */ 
/* memory address, chipside */
#define AGNX_CIR_RXCLIADDR	0x3064	/* receive clientside address */
#define AGNX_CIR_RXDMACTL	0x3068	/* receive dma control */
#define AGNX_CIR_TXCFG		0x3080	/* transmit config */
#define AGNX_CIR_TXMCTL		0x3090 /* Transmit Management Control */
#define		ENABLE_TX_INTERRUPT 0x20
#define		TX_CACHE_LINE	    0x8	
#define AGNX_CIR_TXMSTART	0x3094 /* Transmit Management Start */
#define AGNX_CIR_TXMEND		0x3098 /* Transmit Management End */
#define AGNX_CIR_TXDCTL		0x30a0	/* transmit data control */
/* memeory address, chipset */
#define AGNX_CIR_TXDSTART	0x30a4	/* transmit data start */
#define AGNX_CIR_TXDEND		0x30a8	/* transmit data end */
#define AGNX_CIR_TXMHADDR	0x30b0 /* Transmit Management Hostside Address */
#define AGNX_CIR_TXMCADDR	0x30b4 /* Transmit Management Clientside Address */
#define AGNX_CIR_TXDMACTL	0x30b8	/* transmit dma control */


/* Power Managment Unit */
#define AGNX_PM_BASE		0x3c00	
#define AGNX_PM_PMCTL		0x3c00	/* PM Control*/
#define AGNX_PM_MACMSW		0x3c08 /* MAC Manual Slow Work Enable */
#define AGNX_PM_RFCTL		0x3c0c /* RF Control */
#define AGNX_PM_PHYMW		0x3c14	/* Phy Mannal Work */
#define AGNX_PM_SOFTRST		0x3c18	/* PMU Soft Reset */
#define AGNX_PM_PLLCTL		0x3c1c	/* PMU PLL control*/
#define AGNX_PM_TESTPHY		0x3c24 /* PMU Test Phy */