rf.c

Airgo agn1000系列 无线网卡驱动源码

	reg = agnx_read32(ctl, AGNX_PM_PMCTL);
	reg |= 0x8;
	agnx_write32(ctl, AGNX_PM_PMCTL, reg);

	spi_rc_write(ctl, RF_CHIP0|RF_CHIP1, 0x22);
	udelay(80);
	reg = agnx_read32(ctl, AGNX_SPI_RLSW);


	agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xff);
	agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);

	reg = agnx_read32(ctl, 0xec50);
	reg |= 0x4f;
	agnx_write32(ctl, 0xec50, reg);

	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
	agnx_write32(ctl, 0x11008, 0x1);
	agnx_write32(ctl, 0x1100c, 0x0);
	agnx_write32(ctl, 0x11008, 0x0);
	agnx_write32(ctl, 0xec50, 0xc);

	agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
	agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
	agnx_write32(ctl, 0x11010, 0x6e);
	agnx_write32(ctl, 0x11014, 0x6c);

	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);

	/* Calibrate the Antenna */
	/* antenna_calibrate(priv); */
	/* Calibrate the TxLocalOscillator */
	calibrate_oscillator(priv);

	reg = agnx_read32(ctl, AGNX_PM_PMCTL);
	reg &= ~0x8;
	agnx_write32(ctl, AGNX_PM_PMCTL, reg);
	agnx_write32(ctl, AGNX_GCR_GAININIT, 0xa);
	agnx_write32(ctl, AGNX_GCR_THCD, 0x0);

	agnx_write32(ctl, 0x11018, 0xb);
	agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x0);

	/* Write Frequency to Gain Control Channel */
	agnx_write32(ctl, AGNX_GCR_RXCHANEL, freq);
	/* Write 0x140000/Freq to 0x9c08 */
	reg = 0x140000/freq;
	agnx_write32(ctl, 0x9c08, reg);

	reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
	reg &= ~0x80100030;
	agnx_write32(ctl, AGNX_PM_SOFTRST, reg);

	reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
	reg &= ~0x20009;
	reg |= 0x1;
	agnx_write32(ctl, AGNX_PM_PLLCTL, reg);

	agnx_write32(ctl, AGNX_ACI_MODE, 0x0);

/* FIXME According to Number of Chains: */

/* 			   1. 1: */
/*          1. Write 0x1203 to RF Chip 0 */
/*          2. Write 0x1200 to RF Chips 1 +2  */
/* 			   2. 2: */
/*          1. Write 0x1203 to RF Chip 0 */
/*          2. Write 0x1200 to RF Chip 2 */
/*          3. Write 0x1201 to RF Chip 1  */
/* 			   3. 3: */
/*          1. Write 0x1203 to RF Chip 0 */
/*          2. Write 0x1201 to RF Chip 1 + 2  */
/* 			   4. 4: */
/*          1. Write 0x1203 to RF Chip 0 + 1 */
/*          2. Write 0x1200 to RF Chip 2  */

/* 			   5. 6: */
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1203);
	spi_rf_write(ctl, RF_CHIP2, 0x1201);

	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1000);
	agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);

	/* FIXME Set the Disable Tx interrupt bit in Interrupt Mask 
	   (Or 0x20000 to Interrupt Mask) */
/* 	reg = agnx_read32(ctl, AGNX_INT_MASK); */
/* 	reg |= IRQ_TX_DISABLE; */
/* 	agnx_write32(ctl, AGNX_INT_MASK, reg); */

	agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
	agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);

	/* Configure the Antenna */
	antenna_config(priv);

	/* Write 0x0 to Discovery Mode Enable detect G, B, A packet? */
	agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0);

	reg = agnx_read32(ctl, AGNX_RXM_REQRATE);
	reg |= 0x80000000;
	agnx_write32(ctl, AGNX_RXM_REQRATE, reg);
	agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
	agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);

	/* enable radio on and the power LED */
	reg = agnx_read32(ctl, AGNX_SYSITF_GPIOUT);
	reg &= ~0x1; 
	reg |= 0x2;
	agnx_write32(ctl, AGNX_SYSITF_GPIOUT, reg);

	reg = agnx_read32(ctl, AGNX_TXM_CTL);
	reg |= 0x1;
	agnx_write32(ctl, AGNX_TXM_CTL, reg);
} /* radio_channel_set */

static void base_band_filter_calibrate(struct agnx_priv *priv)
{
	void __iomem *ctl = priv->ctl;

	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1700);
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1001); 
	agnx_write32(ctl, AGNX_GCR_FORCECTLCLK, 0x0);
	spi_rc_write(ctl, RF_CHIP0, 0x27); 
	spi_rc_write(ctl, RF_CHIP1, 0x27); 
	spi_rc_write(ctl, RF_CHIP2, 0x27); 
	agnx_write32(ctl, AGNX_GCR_FORCECTLCLK, 0x1);
}

static void print_offset(struct agnx_priv *priv, u32 chain)
{
	void __iomem *ctl = priv->ctl;
	u32 offset;

	iowrite32((chain), ctl + AGNX_ACI_SELCHAIN);
	udelay(10);
	offset = (ioread32(ctl + AGNX_ACI_OFFSET));
	agnx_dbg("Chain is 0x%x, Offset is 0x%x\n", chain, offset);
}

void print_offsets(struct agnx_priv *priv)
{
	print_offset(priv, 0);
	print_offset(priv, 4);
	print_offset(priv, 1);
	print_offset(priv, 5);
	print_offset(priv, 2);
	print_offset(priv, 6);
}


struct chains {
	u32 cali;		/* calibrate  value*/

#define  NEED_CALIBRATE		0
#define  SUCCESS_CALIBRATE	1
	int status;
};

static void chain_calibrate(struct agnx_priv *priv, struct chains *chains, 
			    unsigned int num)
{
	void __iomem *ctl = priv->ctl;
	u32 calibra = chains[num].cali;

	if (num < 3)
		calibra |= 0x1400;
	else
		calibra |= 0x1500;

	switch (num) {
	case 0:
	case 4:
		spi_rf_write(ctl, RF_CHIP0, calibra);
		break;
	case 1:
	case 5:
		spi_rf_write(ctl, RF_CHIP1, calibra);
		break;
	case 2:
	case 6:
		spi_rf_write(ctl, RF_CHIP2, calibra);
		break;
	default:
		BUG();
	}
} /* chain_calibrate */


static void inline get_calibrete_value(struct agnx_priv *priv, struct chains *chains, 
				       unsigned int num)
{
	void __iomem *ctl = priv->ctl;
	u32 offset;

	iowrite32((num), ctl + AGNX_ACI_SELCHAIN);
	/* FIXME */
	udelay(10);
	offset = (ioread32(ctl + AGNX_ACI_OFFSET));

	if (offset < 0xf) {
		chains[num].status = SUCCESS_CALIBRATE;
		return;
	} 

	if (num == 0 || num == 1 || num == 2) {
		if ( 0 == chains[num].cali)
			chains[num].cali = 0xff;
		else
			chains[num].cali--; 
	} else
		chains[num].cali++; 

	chains[num].status = NEED_CALIBRATE;
}				

static inline void calibra_delay(struct agnx_priv *priv)
{
	void __iomem *ctl = priv->ctl;
	u32 reg;
	unsigned int i = 100;

	wmb();
	while (i--) {
		reg = (ioread32(ctl + AGNX_ACI_STATUS));
		if (reg == 0x4000)
			break;
		udelay(10);
	}
	if (!i)
		printk(PFX "calibration failed\n");
}

void do_calibration(struct agnx_priv *priv)
{
	void __iomem *ctl = priv->ctl;
	struct chains chains[7];
	unsigned int i, j;
	AGNX_TRACE;

	for (i = 0; i < 7; i++) {
		if (i == 3)
			continue;

		chains[i].cali = 0x7f;
		chains[i].status = NEED_CALIBRATE;		
	}

	/* FIXME 0x300 is a magic number */ 
	for (j = 0; j < 0x300; j++) {
		if (chains[0].status == SUCCESS_CALIBRATE && 
		    chains[1].status == SUCCESS_CALIBRATE && 
		    chains[2].status == SUCCESS_CALIBRATE &&
		    chains[4].status == SUCCESS_CALIBRATE &&
		    chains[5].status == SUCCESS_CALIBRATE &&
		    chains[6].status == SUCCESS_CALIBRATE)
			break;
		
		/* Attention, there is no chain 3 */
		for (i = 0; i < 7; i++) {
			if (i == 3)
				continue;
			if (chains[i].status == NEED_CALIBRATE) 
				chain_calibrate(priv, chains, i);			
		}
		/* Write 0x1 to Calibration Measure */
		iowrite32((0x1), ctl + AGNX_ACI_MEASURE);
		calibra_delay(priv);
		
		for (i = 0; i < 7; i++) {
			if (i == 3)
				continue;

			get_calibrete_value(priv, chains, i);
		}
	}
	agnx_dbg("Clibrate times is %d\n", j);
	print_offsets(priv);
} /* do_calibration */

void antenna_calibrate(struct agnx_priv *priv)
{
	void __iomem *ctl = priv->ctl;
	u32 reg;
	AGNX_TRACE;

	agnx_write32(ctl, AGNX_GCR_NLISTANT, 0x3);
	agnx_write32(ctl, AGNX_GCR_NMEASANT, 0x3);
	agnx_write32(ctl, AGNX_GCR_NACTIANT, 0x3);
	agnx_write32(ctl, AGNX_GCR_NCAPTANT, 0x3);

	agnx_write32(ctl, AGNX_GCR_ANTCFG, 0x1f);
	agnx_write32(ctl, AGNX_GCR_BOACT, 0x24);
	agnx_write32(ctl, AGNX_GCR_BOINACT, 0x24);
	agnx_write32(ctl, AGNX_GCR_BODYNA, 0x20);
	agnx_write32(ctl, AGNX_GCR_THD0A, 0x64);
	agnx_write32(ctl, AGNX_GCR_THD0AL, 0x64);
	agnx_write32(ctl, AGNX_GCR_THD0B, 0x46);
	agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 0x3c);
	agnx_write32(ctl, AGNX_GCR_SIGHTH, 0x64);
	agnx_write32(ctl, AGNX_GCR_SIGLTH, 0x30);

	spi_rc_write(ctl, RF_CHIP0, 0x20); 
	/* Fixme */
	udelay(80);
	/*    1. Should read 0x0  */
	reg = agnx_read32(ctl, AGNX_SPI_RLSW);
	if (0x0 != reg)
		printk(KERN_WARNING PFX "Unmatched rf chips result reg = %x\n", reg);
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1000); 

	agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);

	spi_rc_write(ctl, RF_CHIP0, 0x22); 
	udelay(80);
	reg = agnx_read32(ctl, AGNX_SPI_RLSW);
	if (0x0 != reg)
		printk(KERN_WARNING PFX "Unmatched rf chips result reg = %x\n", reg);
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1005); 

	agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
	agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);

	reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
	reg |= 0x1c000032;
	agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
	reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
	reg |= 0x0003f07;
	agnx_write32(ctl, AGNX_PM_PLLCTL, reg);

	reg = agnx_read32(ctl, 0xec50);
	reg |= 0x40;
	agnx_write32(ctl, 0xec50, reg);

	agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xff8);
	agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);

	agnx_write32(ctl, AGNX_GCR_CHAINNUM, 0x6);
	agnx_write32(ctl, 0x19874, 0x0);
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1700); 

	/* Calibrate the BaseBandFilter */
	base_band_filter_calibrate(priv);

	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1002); 
	
	agnx_write32(ctl, AGNX_GCR_GAINSET0, 0x1d);
	agnx_write32(ctl, AGNX_GCR_GAINSET1, 0x1d);
	agnx_write32(ctl, AGNX_GCR_GAINSET2, 0x1d);       
	agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x1);

	agnx_write32(ctl, AGNX_ACI_MODE, 0x1);
	agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);

	agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
	agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);

	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1400); 
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1500); 

	/* Measure Calibration */
	agnx_write32(ctl, AGNX_ACI_MEASURE, 0x1);
	calibra_delay(priv);

	/* do calibration */
	do_calibration(priv);

	agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
	agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
	agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
	agnx_write32(ctl, AGNX_ACI_LEN, 0xf);

	reg = agnx_read32(ctl, AGNX_GCR_GAINSET0);
	reg &= 0xf;
	agnx_write32(ctl, AGNX_GCR_GAINSET0, reg);
	reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
	reg &= 0xf;
	agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
	reg = agnx_read32(ctl, AGNX_GCR_GAINSET2);
	reg &= 0xf;
	agnx_write32(ctl, AGNX_GCR_GAINSET2, reg);

	agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x0);
	disable_receiver(priv);
} /* antenna_calibrate */

void __antenna_calibrate(struct agnx_priv *priv)
{
	void __iomem *ctl = priv->ctl;
	u32 reg;

	/* Calibrate the BaseBandFilter */
	/* base_band_filter_calibrate(priv); */
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1002);


	agnx_write32(ctl, AGNX_GCR_GAINSET0, 0x1d);
	agnx_write32(ctl, AGNX_GCR_GAINSET1, 0x1d);
	agnx_write32(ctl, AGNX_GCR_GAINSET2, 0x1d);

	agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x1);

	agnx_write32(ctl, AGNX_ACI_MODE, 0x1);
	agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);


	agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
	agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1400);
	spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1500);
	/* Measure Calibration */
	agnx_write32(ctl, AGNX_ACI_MEASURE, 0x1);
	calibra_delay(priv);
	do_calibration(priv);
	agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);

	agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
	agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);

	agnx_write32(ctl, AGNX_ACI_LEN, 0xf);

	reg = agnx_read32(ctl, AGNX_GCR_GAINSET0);
	reg &= 0xf;
	agnx_write32(ctl, AGNX_GCR_GAINSET0, reg);
	reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
	reg &= 0xf;
	agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
	reg = agnx_read32(ctl, AGNX_GCR_GAINSET2);
	reg &= 0xf;
	agnx_write32(ctl, AGNX_GCR_GAINSET2, reg);


	agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x0);

	/* Write 0x3 Gain Control Discovery Mode */
	enable_receiver(priv);
}

int agnx_set_channel(struct agnx_priv *priv, unsigned int channel)
{
	AGNX_TRACE;

	agnx_dbg("Channel is %d %s\n", channel, __func__);
	radio_channel_set(priv, channel);
	return 0;	
}