📄 agnx.h
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#ifndef AGNX_H_#define AGNX_H_#include "xmit.h"#define PFX KBUILD_MODNAME ": "static inline u32 agnx_read32(void __iomem *mem_region, u32 offset){ return ioread32(mem_region + offset);}static inline void agnx_write32(void __iomem *mem_region, u32 offset, u32 val){ iowrite32(val, mem_region + offset);}#define CHAN4G(_channel, _freq, _flags) { \ .band = IEEE80211_BAND_2GHZ, \ .center_freq = (_freq), \ .hw_value = (_channel), \ .flags = (_flags), \ .max_antenna_gain = 0, \ .max_power = 30, \}static struct ieee80211_channel agnx_2ghz_channels[] = { CHAN4G(1, 2412, 0 ), CHAN4G(2, 2417, 0 ), CHAN4G(3, 2422, 0 ), CHAN4G(4, 2427, 0 ), CHAN4G(5, 2432, 0 ), CHAN4G(6, 2437, 0 ), CHAN4G(7, 2442, 0 ), CHAN4G(8, 2447, 0 ), CHAN4G(9, 2452, 0 ), CHAN4G(10, 2457, 0), CHAN4G(11, 2462, 0), CHAN4G(12, 2467, 0), CHAN4G(13, 2472, 0), CHAN4G(14, 2484, 0),};static struct ieee80211_rate __agnx_ratetable[] = { { .bitrate = 10, .hw_value = 1, }, { .bitrate = 20, .hw_value = 2, }, { .bitrate = 55, .hw_value = 3, }, { .bitrate = 110, .hw_value = 4, }, { .bitrate = 60, .hw_value = 0xB, }, { .bitrate = 90, .hw_value = 0xF, }, { .bitrate = 120, .hw_value = 0xA }, { .bitrate = 180, .hw_value = 0xE, }, { .bitrate = 240, .hw_value = 0xd, }, { .bitrate = 360, .hw_value = 0xD, }, { .bitrate = 480, .hw_value = 0x8, }, { .bitrate = 540, .hw_value = 0xC, },};#define agnx_g_ratetable (__agnx_ratetable + 0)#define agnx_g_ratetable_size 12/* * Define our G band * Have to define here, because IEEE80211 adds stuff to it */static const struct ieee80211_supported_band agnx_band_2GHz = { .band = IEEE80211_BAND_2GHZ, .channels = agnx_2ghz_channels, .n_channels = ARRAY_SIZE(agnx_2ghz_channels), .bitrates = agnx_g_ratetable, .n_bitrates = agnx_g_ratetable_size,};#define NUM_DRIVE_MODES 2/* Agnx operate mode */enum { AGNX_MODE_80211A, AGNX_MODE_80211A_OOB, AGNX_MODE_80211A_MIMO, AGNX_MODE_80211B_SHORT, AGNX_MODE_80211B_LONG, AGNX_MODE_80211G, AGNX_MODE_80211G_OOB, AGNX_MODE_80211G_MIMO, };enum { AGNX_UNINIT, AGNX_START, AGNX_STOP,};struct agnx_priv { struct pci_dev *pdev; struct ieee80211_hw *hw; spinlock_t lock; struct mutex mutex; unsigned int init_status; void __iomem *ctl; /* pointer to base ram address */ void __iomem *data; /* pointer to mem region #2 */ struct agnx_ring rx; struct agnx_ring txm; struct agnx_ring txd; /* Need volatile? */ u32 irq_status; struct delayed_work periodic_work; /* Periodic tasks like recalibrate*/ struct ieee80211_low_level_stats stats;// unsigned int phymode; int mode; int channel; u8 bssid[ETH_ALEN]; u8 ssid[32]; size_t ssid_len; u8 mac_addr[ETH_ALEN]; u8 revid; struct ieee80211_supported_band band; // Registerd/Unregistered flag u8 mac80211_registered;};#define AGNX_CHAINS_MAX 6#define AGNX_PERIODIC_DELAY 60000 /* unit: ms */#define LOCAL_STAID 0 /* the station entry for the card itself */#define BSSID_STAID 1 /* the station entry for the bsssid AP */#define spi_delay() udelay(40)#define eeprom_delay() udelay(40)#define routing_table_delay() udelay(50)/* PDU pool MEM region #2 */#define AGNX_PDUPOOL 0x40000 /* PDU pool */#define AGNX_PDUPOOL_SIZE 0x8000 /* PDU pool size*/#define AGNX_PDU_TX_WQ 0x41000 /* PDU list TX workqueue */#define AGNX_PDU_FREE 0x41800 /* Free Pool */#define PDU_SIZE 0x80 /* Free Pool node size */#define PDU_FREE_CNT 0xd0 /* Free pool node count *//* RF stuffs */extern void rf_chips_init(struct agnx_priv *priv);extern void spi_rc_write(void __iomem *mem_region, u32 chip_ids, u32 sw);extern void calibrate_oscillator(struct agnx_priv *priv);extern void do_calibration(struct agnx_priv *priv);extern void antenna_calibrate(struct agnx_priv *priv);extern void __antenna_calibrate(struct agnx_priv *priv);extern void print_offsets(struct agnx_priv *priv);extern int agnx_set_channel(struct agnx_priv *priv, unsigned int channel);#endif /* AGNX_H_ */
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