leap-year.v

一个FIFO设计的例子

module leap_year(out,y,cont,in,reset,clk);
  output [15:0]   out;
  output          y;
  input  [15:0]   in;
  input           cont;
  input           reset,clk;
  reg             y;
  wire   [7:0]    out1;
  wire   [7:0]    out2;
  wire   [15:0]   out={out2,out1};
  wire            co1;
  
   count100 M1 (out1,co1,cont,in[7:0],reset,clk);

   count100 M2 (out2,,cont,in[15:8],reset,co1);

   always@(out1 or out2)
     if((out2[4]==0&&(out2[3:0]==0||out2[3:0]==4||out2[3:0]==8)||out2[4]==1&&(out2[3:0]==2||out2[3:0]==6))&&out1==0)
	         y=1;
	 else if(out1==0) y=0;
	 else if(out1[4]==0&&(out1[3:0]==0||out1[3:0]==4||out1[3:0]==8)||out1[4]==1&&(out1[3:0]==2||out1[3:0]==6)) y=1;
	 else y=0;

endmodule

module count100(out,co,cont,in,reset,clk);
  output [7:0]  out;
  output        co;
  input  [7:0]  in;
  input         cont;
  input         reset,clk;
  reg    [3:0]  q1,q2;
  wire   [7:0]  out={q2,q1};
  reg           co;

   always@(posedge clk or posedge reset or posedge cont)
    begin	  
	  if(reset)              begin {q2,q1}<=0;co<=0;end
	  else if(cont)          begin {q2,q1}<=in;co<=0;end
	  else if(q2>9||q1>9)    begin {q2,q1}<=0;co<=0;end
	  else if(q2==9&&q1==9)  begin co<=1;q2<=0;q1<=0;end
	  else if(q1==9)         begin q2<=q2+1;q1<=0;co<=0;end
	  else                   begin q1<=q1+1;co<=0;end
	end

endmodule