📄 bj.map.rpt
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+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; bj.vhd ; yes ; Other ; E:/QuartueII/bj/bj.vhd ;
+----------------------------------+-----------------+-----------+------------------------------+
+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------+
; Resource ; Usage ;
+---------------------------------------------+----------+
; Total logic elements ; 4 ;
; -- Combinational with no register ; 0 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 4 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 4 ;
; -- 2 input functions ; 0 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 4 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 4 ;
; ; ;
; Total registers ; 4 ;
; I/O pins ; 9 ;
; Maximum fan-out node ; director ;
; Maximum fan-out ; 4 ;
; Total fan-out ; 24 ;
; Average fan-out ; 1.85 ;
+---------------------------------------------+----------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |bj ; 4 (4) ; 4 ; 0 ; 9 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |bj ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+--------------------------------------------------------------------------+
; State Machine - |bj|cur_state ;
+--------------+--------------+--------------+--------------+--------------+
; Name ; cur_state.s3 ; cur_state.s2 ; cur_state.s1 ; cur_state.s0 ;
+--------------+--------------+--------------+--------------+--------------+
; cur_state.s0 ; 0 ; 0 ; 0 ; 0 ;
; cur_state.s1 ; 0 ; 0 ; 1 ; 1 ;
; cur_state.s2 ; 0 ; 1 ; 0 ; 1 ;
; cur_state.s3 ; 1 ; 0 ; 0 ; 1 ;
+--------------+--------------+--------------+--------------+--------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 4 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 4 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sat Nov 08 11:19:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bj -c bj
Warning: Using design file bj.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: bj-m
Info: Found entity 1: bj
Info: Elaborating entity "bj" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at bj.vhd(22): inferring latch(es) for signal or variable "temp", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at bj.vhd(22): inferring latch(es) for signal or variable "nex_state", which holds its previous value in one or more paths through the process
Info: State machine "|bj|cur_state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|bj|cur_state"
Info: Encoding result for state machine "|bj|cur_state"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "cur_state.s3"
Info: Encoded state bit "cur_state.s2"
Info: Encoded state bit "cur_state.s1"
Info: Encoded state bit "cur_state.s0"
Info: State "|bj|cur_state.s0" uses code string "0000"
Info: State "|bj|cur_state.s1" uses code string "0011"
Info: State "|bj|cur_state.s2" uses code string "0101"
Info: State "|bj|cur_state.s3" uses code string "1001"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "ena" stuck at VCC
Warning (13410): Pin "enb" stuck at VCC
Info: Implemented 13 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 6 output pins
Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Allocated 156 megabytes of memory during processing
Info: Processing ended: Sat Nov 08 11:19:59 2008
Info: Elapsed time: 00:00:07
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