prev_cmp_bj.tan.qmsg

四位单相的步进电机程序,经过编译和仿真.

{ "Info" "ITDB_TSU_RESULT" "cur_state.s3 director clk 3.295 ns register " "Info: tsu for register \"cur_state.s3\" (data pin = \"director\", clock pin = \"clk\") is 3.295 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.537 ns + Longest pin register " "Info: + Longest pin to register delay is 5.537 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns director 1 PIN PIN_237 4 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_237; Fanout = 4; PIN Node = 'director'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { director } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.935 ns) + CELL(0.467 ns) 5.537 ns cur_state.s3 2 REG LC_X2_Y17_N5 3 " "Info: 2: + IC(3.935 ns) + CELL(0.467 ns) = 5.537 ns; Loc. = LC_X2_Y17_N5; Fanout = 3; REG Node = 'cur_state.s3'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.402 ns" { director cur_state.s3 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.602 ns ( 28.93 % ) " "Info: Total cell delay = 1.602 ns ( 28.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.935 ns ( 71.07 % ) " "Info: Total interconnect delay = 3.935 ns ( 71.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.537 ns" { director cur_state.s3 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.537 ns" { director {} director~out0 {} cur_state.s3 {} } { 0.000ns 0.000ns 3.935ns } { 0.000ns 1.135ns 0.467ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.271 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns cur_state.s3 2 REG LC_X2_Y17_N5 3 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y17_N5; Fanout = 3; REG Node = 'cur_state.s3'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { clk cur_state.s3 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s3 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s3 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.537 ns" { director cur_state.s3 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.537 ns" { director {} director~out0 {} cur_state.s3 {} } { 0.000ns 0.000ns 3.935ns } { 0.000ns 1.135ns 0.467ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s3 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s3 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk a cur_state.s0 6.380 ns register " "Info: tco from clock \"clk\" to destination pin \"a\" through register \"cur_state.s0\" is 6.380 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.271 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns cur_state.s0 2 REG LC_X2_Y17_N6 3 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y17_N6; Fanout = 3; REG Node = 'cur_state.s0'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { clk cur_state.s0 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s0 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.936 ns + Longest register pin " "Info: + Longest register to pin delay is 3.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cur_state.s0 1 REG LC_X2_Y17_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N6; Fanout = 3; REG Node = 'cur_state.s0'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { cur_state.s0 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.314 ns) + CELL(1.622 ns) 3.936 ns a 2 PIN PIN_62 0 " "Info: 2: + IC(2.314 ns) + CELL(1.622 ns) = 3.936 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'a'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.936 ns" { cur_state.s0 a } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 41.21 % ) " "Info: Total cell delay = 1.622 ns ( 41.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.314 ns ( 58.79 % ) " "Info: Total interconnect delay = 2.314 ns ( 58.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.936 ns" { cur_state.s0 a } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.936 ns" { cur_state.s0 {} a {} } { 0.000ns 2.314ns } { 0.000ns 1.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s0 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.936 ns" { cur_state.s0 a } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.936 ns" { cur_state.s0 {} a {} } { 0.000ns 2.314ns } { 0.000ns 1.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cur_state.s2 director clk -3.252 ns register " "Info: th for register \"cur_state.s2\" (data pin = \"director\", clock pin = \"clk\") is -3.252 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.271 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns cur_state.s2 2 REG LC_X2_Y17_N2 3 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y17_N2; Fanout = 3; REG Node = 'cur_state.s2'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { clk cur_state.s2 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s2 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s2 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.535 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns director 1 PIN PIN_237 4 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_237; Fanout = 4; PIN Node = 'director'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { director } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.933 ns) + CELL(0.467 ns) 5.535 ns cur_state.s2 2 REG LC_X2_Y17_N2 3 " "Info: 2: + IC(3.933 ns) + CELL(0.467 ns) = 5.535 ns; Loc. = LC_X2_Y17_N2; Fanout = 3; REG Node = 'cur_state.s2'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { director cur_state.s2 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.602 ns ( 28.94 % ) " "Info: Total cell delay = 1.602 ns ( 28.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.933 ns ( 71.06 % ) " "Info: Total interconnect delay = 3.933 ns ( 71.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.535 ns" { director cur_state.s2 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.535 ns" { director {} director~out0 {} cur_state.s2 {} } { 0.000ns 0.000ns 3.933ns } { 0.000ns 1.135ns 0.467ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s2 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s2 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.535 ns" { director cur_state.s2 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "5.535 ns" { director {} director~out0 {} cur_state.s2 {} } { 0.000ns 0.000ns 3.933ns } { 0.000ns 1.135ns 0.467ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 08 11:19:10 2008 " "Info: Processing ended: Sat Nov 08 11:19:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}