bj.vhd.bak

四位单相的步进电机程序,经过编译和仿真.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bj IS
 PORT(clk,stop,director,rst:IN STD_LOGIC;
    a,b,c,d,ena,enb:OUT STD_LOGIC);
END bj;
ARCHITECTURE m OF bj IS
  SIGNAL temp:std_logic_vector(5 DOWNTO 0);
  TYPE states IS(s0,s1,s2,s3);
  SIGNAL cur_state,nex_state:states;
BEGIN
  p1:PROCESS(clk,rst)
    BEGIN
       IF(rst='1') THEN
         cur_state<=s0;

       ELSIF(clk'EVENT AND clk='1') THEN
         cur_state<=nex_state;
       END IF;
   END PROCESS p1;
 p2:PROCESS(cur_state,director)
      BEGIN
        IF(director='1') THEN
            CASE cur_state IS
              WHEN s0=>temp<="100011";nex_state<=s1;
              WHEN s1=>temp<="010011";nex_state<=s2;
              WHEN s2=>temp<="001011";nex_state<=s3;
              WHEN S3=>temp<="000111";nex_state<=s0;
              WHEN OTHERS=>temp<="000000";nex_state<=s0;
           END CASE;
        ELSIF(director='0') THEN 
            CASE cur_state IS
              WHEN s0=>temp<="100011";nex_state<=s3;
              WHEN s3=>temp<="000111";nex_state<=s2;
              WHEN s2=>temp<="001011";nex_state<=s1;
              WHEN s1=>temp<="010011";nex_state<=s0;
              WHEN OTHERS=>temp<="000000";nex_state<=s0;
           END CASE;
        END IF;
    END PROCESS p2;
   a<=temp(5);b<=temp(4);c<=temp(3);d<=temp(2);ena<=temp(1);enb<=temp(0);
END m;