bj.tan.rpt

四位单相的步进电机程序,经过编译和仿真.

+-------+--------------+------------+----------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From     ; To           ; To Clock ;
+-------+--------------+------------+----------+--------------+----------+
; N/A   ; None         ; 3.368 ns   ; director ; cur_state.s0 ; clk      ;
; N/A   ; None         ; 3.367 ns   ; director ; cur_state.s1 ; clk      ;
; N/A   ; None         ; 3.367 ns   ; director ; cur_state.s3 ; clk      ;
; N/A   ; None         ; 3.365 ns   ; director ; cur_state.s2 ; clk      ;
+-------+--------------+------------+----------+--------------+----------+


+--------------------------------------------------------------------+
; tco                                                                ;
+-------+--------------+------------+--------------+----+------------+
; Slack ; Required tco ; Actual tco ; From         ; To ; From Clock ;
+-------+--------------+------------+--------------+----+------------+
; N/A   ; None         ; 5.155 ns   ; cur_state.s1 ; b  ; clk        ;
; N/A   ; None         ; 5.060 ns   ; cur_state.s0 ; a  ; clk        ;
; N/A   ; None         ; 5.058 ns   ; cur_state.s2 ; c  ; clk        ;
; N/A   ; None         ; 5.057 ns   ; cur_state.s3 ; d  ; clk        ;
+-------+--------------+------------+--------------+----+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+----------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To           ; To Clock ;
+---------------+-------------+-----------+----------+--------------+----------+
; N/A           ; None        ; -3.324 ns ; director ; cur_state.s2 ; clk      ;
; N/A           ; None        ; -3.326 ns ; director ; cur_state.s1 ; clk      ;
; N/A           ; None        ; -3.326 ns ; director ; cur_state.s3 ; clk      ;
; N/A           ; None        ; -3.327 ns ; director ; cur_state.s0 ; clk      ;
+---------------+-------------+-----------+----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Nov 08 11:20:18 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bj -c bj --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "cur_state.s3" and destination register "cur_state.s0"
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.882 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y20_N0; Fanout = 3; REG Node = 'cur_state.s3'
            Info: 2: + IC(0.415 ns) + CELL(0.467 ns) = 0.882 ns; Loc. = LC_X2_Y20_N5; Fanout = 3; REG Node = 'cur_state.s0'
            Info: Total cell delay = 0.467 ns ( 52.95 % )
            Info: Total interconnect delay = 0.415 ns ( 47.05 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.271 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y20_N5; Fanout = 3; REG Node = 'cur_state.s0'
                Info: Total cell delay = 1.677 ns ( 73.84 % )
                Info: Total interconnect delay = 0.594 ns ( 26.16 % )
            Info: - Longest clock path from clock "clk" to source register is 2.271 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y20_N0; Fanout = 3; REG Node = 'cur_state.s3'
                Info: Total cell delay = 1.677 ns ( 73.84 % )
                Info: Total interconnect delay = 0.594 ns ( 26.16 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "cur_state.s0" (data pin = "director", clock pin = "clk") is 3.368 ns
    Info: + Longest pin to register delay is 5.610 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_239; Fanout = 4; PIN Node = 'director'
        Info: 2: + IC(3.907 ns) + CELL(0.568 ns) = 5.610 ns; Loc. = LC_X2_Y20_N5; Fanout = 3; REG Node = 'cur_state.s0'
        Info: Total cell delay = 1.703 ns ( 30.36 % )
        Info: Total interconnect delay = 3.907 ns ( 69.64 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.271 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y20_N5; Fanout = 3; REG Node = 'cur_state.s0'
        Info: Total cell delay = 1.677 ns ( 73.84 % )
        Info: Total interconnect delay = 0.594 ns ( 26.16 % )
Info: tco from clock "clk" to destination pin "b" through register "cur_state.s1" is 5.155 ns
    Info: + Longest clock path from clock "clk" to source register is 2.271 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y20_N3; Fanout = 3; REG Node = 'cur_state.s1'
        Info: Total cell delay = 1.677 ns ( 73.84 % )
        Info: Total interconnect delay = 0.594 ns ( 26.16 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 2.711 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y20_N3; Fanout = 3; REG Node = 'cur_state.s1'
        Info: 2: + IC(1.077 ns) + CELL(1.634 ns) = 2.711 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'b'
        Info: Total cell delay = 1.634 ns ( 60.27 % )
        Info: Total interconnect delay = 1.077 ns ( 39.73 % )
Info: th for register "cur_state.s2" (data pin = "director", clock pin = "clk") is -3.324 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.271 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y20_N2; Fanout = 3; REG Node = 'cur_state.s2'
        Info: Total cell delay = 1.677 ns ( 73.84 % )
        Info: Total interconnect delay = 0.594 ns ( 26.16 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.607 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_239; Fanout = 4; PIN Node = 'director'
        Info: 2: + IC(3.904 ns) + CELL(0.568 ns) = 5.607 ns; Loc. = LC_X2_Y20_N2; Fanout = 3; REG Node = 'cur_state.s2'
        Info: Total cell delay = 1.703 ns ( 30.37 % )
        Info: Total interconnect delay = 3.904 ns ( 69.63 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Sat Nov 08 11:20:19 2008
    Info: Elapsed time: 00:00:01