shiyan6.vhd

一个8位的十进制频率计数器,功能经过测试.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TESTCTL  IS
PORT(CLKK: IN STD_LOGIC;
     CNT_EN,RST_CNT,LOAD:OUT STD_LOGIC);
END TESTCTL;
ARCHITECTURE BEHAVIOR OF TESTCTL IS 
SIGNAL div2clk:STD_LOGIC;
BEGIN
  PROCESS(CLKK)
   BEGIN
    IF CLKK'EVENT AND CLKK='1' THEN 
       div2clk<=NOT div2clk;
    END IF;
  END PROCESS; 
PROCESS(CLKK,div2clk)
  BEGIN
IF (CLKK='0' AND div2clk='0') THEN 
        RST_CNT<='1';
     ELSE RST_CNT<='0';
    END IF;
END PROCESS;
LOAD<=NOT div2clk;CNT_EN<=div2clk;
END BEHAVIOR; 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
   PORT(CLK,RST,ENA:IN STD_LOGIC;
             OUTY:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
             COUT:OUT STD_LOGIC);
END CNT10;
ARCHITECTURE JISHU OF CNT10 IS
    SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
    PROCESS(CLK,RST,ENA)
       BEGIN
         IF(RST='1') THEN
            CQI<=(OTHERS=>'0');
         ELSIF(CLK'EVENT AND CLK='1') THEN
              IF(ENA='1') THEN
                IF(CQI="1001") THEN
                    CQI<="0000";
                    COUT<='1';
                ELSE
                    CQI<=CQI+1;
                    COUT<='0';
                END IF;
              END IF;
          END IF;
    END PROCESS;
        OUTY<=CQI;
END JISHU;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG4B IS
  PORT(LOAD:IN STD_LOGIC;
       DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END REG4B;
ARCHITECTURE XIANSHI OF REG4B IS
  BEGIN
    PROCESS(LOAD,DIN)
      BEGIN
        IF(LOAD'EVENT AND LOAD='1') THEN
            DOUT<=DIN;
        END IF;
     END PROCESS;
END XIANSHI; 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIYAN6 IS
  PORT(CLK:IN STD_LOGIC;
       fin:IN STD_LOGIC;
     dout:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     coutt:out std_logic);
END SHIYAN6;
ARCHITECTURE M OF SHIYAN6 IS
 SIGNAL cnt_ent,rst_cntt,loadt:STD_LOGIC;
 SIGNAL dout1,dout2,dout3,dout4,dout5,dout6,dout7,dout8:STD_LOGIC_VECTOR(3 DOWNTO 0);
 SIGNAL cout1,cout2,cout3,cout4,cout5,cout6,cout7:STD_LOGIC;
  COMPONENT TESTCTL
     PORT(CLKK:IN STD_LOGIC;
          CNT_EN,RST_CNT,LOAD:OUT STD_LOGIC);
  END COMPONENT;
   COMPONENT CNT10
      PORT(CLK,RST,ENA:IN STD_LOGIC;
             OUTY:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
              COUT:OUT STD_LOGIC);
  END COMPONENT;
    COMPONENT REG4B
       PORT(LOAD:IN STD_LOGIC;
           DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
  END COMPONENT;
BEGIN
   U1:TESTCTL PORT MAP(CLK,cnt_ent,rst_cntt,loadt);
   U2:CNT10 PORT MAP(fin,rst_cntt,cnt_ent,dout1,cout1);
   U3:CNT10 PORT MAP(cout1,rst_cntt,cnt_ent,dout2,cout2);
   U4:CNT10 PORT MAP(cout2,rst_cntt,cnt_ent,dout3,cout3);
   U5:CNT10 PORT MAP(cout3,rst_cntt,cnt_ent,dout4,cout4);
   U6:CNT10 PORT MAP(cout4,rst_cntt,cnt_ent,dout5,cout5);
   U7:CNT10 PORT MAP(cout5,rst_cntt,cnt_ent,dout6,cout6);
   U8:CNT10 PORT MAP(cout6,rst_cntt,cnt_ent,dout7,cout7);
   U9:CNT10 PORT MAP(cout7,rst_cntt,cnt_ent,dout8,coutt);
   U10:REG4B PORT MAP(loadt,dout1,dout(3 downto 0));
   U11:REG4B PORT MAP(loadt,dout2,dout(7 downto 4));
   U12:REG4B PORT MAP(loadt,dout3,dout(11 downto 8));
   U13:REG4B PORT MAP(loadt,dout4,dout(15 downto 12));
   U14:REG4B PORT MAP(loadt,dout5,dout(19 downto 16));
   U15:REG4B PORT MAP(loadt,dout6,dout(23 downto 20));
   U16:REG4B PORT MAP(loadt,dout7,dout(27 downto 24));
   U17:REG4B PORT MAP(loadt,dout8,dout(31 downto 28)); 
END M;