reg2.vhd

来自「实现电子密码锁的各项功能,经过编译和仿真」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
 entity Reg2 is
    port(q_temp:in std_logic_vector(7 downto 0);
          clk2:in std_logic;
             b:out std_logic_vector(7 downto 0));
     end Reg2;
    architecture two of Reg2 is
        begin 
        process(clk2)
          begin 
           if clk2'event and clk2='1' then 
                 b<=q_temp;
            end if;
        end process;
    end two;